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PDF APW7062B Data sheet ( Hoja de datos )
| Número de pieza | APW7062B | |
| Descripción | Synchronous Buck PWM Controller | |
| Fabricantes | Anpec Electronics Coropration | |
| Logotipo |  |
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APW7062B
Features
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- Full 0–100% Duty Ratio
www.DataSheet4U.com
• Excellent Output Voltage Regulation
- 0.8V Internal Reference
- ± 1% Over Line Voltage and Temperature
• Over Current Fault Monitor
- Uses Upper MOSFETs RDS (ON)
• Converter Can Source and Sink Current
• Small Converter Size
- 200kHz Free-Running Oscillator
- Programmable from 70kHz to 800kHz
• 14-Lead SOIC Package
• Lead Free Available (RoHS Compliant)
Applications
• Graphic Cards
• DDR Memory Power Supply
• DDR Memory Termination Voltage
• Low-Voltage Distributed Power Supplies
Synchronous Buck PWM Controller
General Description
The APW7062B is a voltage mode, synchronous PWM
controller which drives dual N-Channel MOSFETs. It
integrates the control, monitoring and protection func-
tions into a single package, provides one controlled
power outputs with under-voltage and over-current
protection.
APW7062B provide excellent regulation for output load
variation. An internal 0.8V temperature-compensated
reference voltage is designed to meet the requirement
of low output voltage applications. It includes a 200kHz
free-running triangle-wave oscillator that is adjustable
from 70kHz to 800kHz.
The power-on-reset (POR) circuit monitors the VCC,
EN, OCSET input voltage to start-up or shutdown the
IC. The over-current protection (OCP) monitors the
output current by using the voltage drop across the
upper MOSFET’s RDS(ON), eliminating the need for a
current sensing resistor. The under-voltage protection
(UVP) monitors the voltage of FB pin for short-circuit
protection.
The over-current protection trip cycle the soft-start func-
tion until the fault events be removed. Under-voltage
protection will shutdown the IC directly.
Pinouts
RT
OCSET
SS
COMP
FB
EN
GND
1
2
3
4
5
6
7
14 VCC
13 PVCC
12 LGATE
11 PGND
10 BOOT
9 UGATE
8 PHASE
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
1
www.anpec.com.tw
1 page  
APW7062B
Functional Pin Description
RT (Pin1)
This pin can adjust the switching frequency. Connect
a resistor from RT to GND for increasing the switching
frequency:
FS
=
200kHz
+
4.15 ×106
RT
(RT to GND,FS = 200kHz to 400kHz)
www.DataSheet4U.com
Conversely, connect a resistor from RT to VCC for de-
creasing the switching frequency:
FS
=
200kHz
-
3.51 × 10 7
RT
(RT to VCC,FS = 200kHz to 75kHz)
OCSET (Pin2)
This pin serves two functions: a shutdown control and
the setting of over current limit threshold. Pulling this
pin below 1.27V will shutdown the controller, forcing
the UGATE and LGATE signals to be at 0V.
A resistor (Rocset) connected between this pin and the
drain of the high side MOSFET will determine the over
current limit. An internal 200uA current source will
flow through this resistor, creating a voltage drop,
which will be compared with the voltage across the
high side MOSFET. The threshold of the over current
limit is therefore given by:
( )IPEAK = IOCSET 200uA R× OCSET
RDS(ON)
To avoid noise interference from switching transient, a
delay time is designed in the OCP comparator.
The over current protection is active only when the
high side MOSFET is turned on longer than 300ns.
SS (Pin3)
Connect a capacitor from the pin to GND to set the
soft-start interval of the converter. An internal 10uA
current source charges this capacitor to 5.8V. The
SS voltage clamps the error amplifier output, and Fig-
ure1 shows the soft-start interval. At t1, the SS volt-
age reaches the valley of the oscillator’s triangle wave.
The PWM comparator starts to generate a PWM sig-
nal to control logic, and the output is rising rapidly.
Until the output is in regulation at t2, the clamp on the
COMP is released. This method provides a rapid and
controlled output voltage rise.
When over current protection occurs, the VOUT is
shutdown, and re-soft-start again, if the over current
condition still exists in soft-start , the VOUT is
shutdowned again, after the SS reaches 4.5V, the SS
is discharged to zero. The soft-start is recurring until
the over current condition is eliminated.
VO L TAGE
VSOFT STAR T
VOSC (M IN)
VSS= 1 .2 V
VO U T
Erro r Am p
Ou tput
t0 t1
t2 t3
TIME
FIGURE1. SOFT-START INTERVAL
It2
=
CSS
SS
× (VOSC(MIN)+
t1)
= − = × ×tSoftStart t3 t2
CSS V OUT SteadyState ∆VOSC
ISS VIN
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
5
www.anpec.com.tw
5 Page 
APW7062B
Application Information
Component Selection Guidelines
∆VOUT = IRIPPLE x ESR
Output Capacitor Selection
The selection of COUT is determined by the required
effective series resistance (ESR) and voltage rating
rather than the actual capacitance requirement. There-
www.DataSheet4U.cfoomre select high performance low ESR capacitors that
are intended for switching regulator applications. In
some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capaci-
tors manufacturer.
Input Capacitor Selection
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is ap-
proximately IOUT/2 , where IOUT is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer.
For high frequency decoupling, a ceramic capacitor
between 0.1uF to 1uF can be connected between VCC
and ground pin.
Inductor Selection
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will trans-
late into lower output ripple voltage. The ripple current
and ripple voltage can be approximated by:
where Fs is the switching frequency of the regulator.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple cur-
rent and vice versa. The maximum ripple current oc-
curs at the maximum input voltage. A good starting
point is to choose the ripple current to be approxi-
mately 30% of the maximum output current.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
type of inductors, especially core that is make of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
Compensation
The output LC filter introduces a double pole, which
contributes with –40dB/decade gain slope and 180
degrees phase shift in the control loop. A compensa-
tion network between COMP pin and ground should
be added. The simplest loop compensation network
is shown in Fig. 4.
The output LC filter consists of the output inductor
and output capacitors. The transfer function of the LC
filter is given by:
GAINLC =
1+ s × ESR × COUT
s2 × L × COUT + s × ESR + 1
IRIPPLE =
VIN - VOUT
Fs x L
x
VOUT
VIN
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet APW7062B.PDF ] | |
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