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PDF CY2SSTV16857 Data sheet ( Hoja de datos )
| Número de pieza | CY2SSTV16857 | |
| Descripción | 14-Bit Regstered Buffer PC2700-/PC3200-Compliant | |
| Fabricantes | SpectraLinear | |
| Logotipo |  |
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CY2SSTV16857
14-Bit Registered Buffer PC2700-/PC3200-Compliant
Features
• Differential Clock Inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET pin
• Output drivers have controlled edge rates, so no
www.DataSheete4xUt.ecronmal resistors are required
• Two KV ESD protection
• Latch-up performance exceeds 100 mA: JESD78, Class II
• Conforms to JEDEC STD (JESD82-3) for buffered DDR
DIMMs
• 48-pin TSSOP
Description
This 14-bit registered buffer is designed specifically for 2.3V to
2.7V VDD operation and is characterized for operation from
0°C to + 85°C.
All inputs are compatible with the JEDEC Standard for
SSTL_2, except the LVCMOS reset (RESET) input. All outputs
are SSTL_2, Class II-compatible.
The SSTV16857 operates from a differential clock (CLK and
CLK). Data is measured at the crossing of CLK going HIGH,
and CLK going LOW.
When RESET is LOW, the differential input receivers are
disabled, and undriven (floating) data, clock, and REF voltage
inputs are allowed. In addition, when RESET is LOW, all
registers are reset and all outputs force to the LOW state. The
LVCMOS RESET input must always be held at a valid logic
HIGH or LOW level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the LOW
state during power-up.
In the DDR registered DIMM application, RESET is specified
to be completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven LOW quickly, relative to the time to
disable the differential input receivers, thus ensuring no
glitches on the output. However, when coming out of reset, the
register will become active quickly, relative to the time to
enable the differential input receivers. As long as the data
inputs are low, and the clock is stable during the time from the
LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design must ensure that the outputs will
remain LOW.
Block Diagram
Pin Configuration
RESET
CLK
CLK
VREF
D1
1D
C1 Q1
R
To 13 Other Channels
Q1
Q2
VSS
VDDQ
Q3
Q4
Q5
VSS
VDDQ
Q6
Q7
VDDQ
VSS
Q8
Q9
VDDQ
VSS
Q10
Q11
Q12
VDDQ
VSS
Q13
Q14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 D1
47 D2
46 VSS
45 VDD
44 D3
43 D4
42 D5
41 D6
40 D7
39 CLK
38 CLK
37 VDD
36 VSS
35 VREF
34 RESET
33 D8
32 D9
31 D10
30 D11
29 D12
28 VDD
27 VSS
26 D13
25 D14
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 7
www.SpectraLinear.com
1 page  
CY2SSTV16857
Table 3. AC Output Electrical Specifications (VDD = 2.5V VDC ± 5%, Temperature = 0°C to +85°C)
Parameter
Description
Condition
VDD = 2.5V ± 0.2V
Min.
Max.
FMAX
TDEL
Propagation Delay from CLK/CLK Q
to Q
280
1.1 2.8
TPHL
TR
TF
RESET
Rise Time
Fall time
Q
Any Q
Any Q
4.3
0.85 4
1.0 4
www.DataSheOetu4Utp.cuomt Buffer Characteristics
Unit
ns
ns
V/ns
V/ns
Table 4. Output Buffer Voltage vs. Current (V/I) Characteristics
Voltage (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Pull-Down
Min I (mA)
Max I (mA)
00
6 13
10 25
15 38
19 49
23 60
27 71
30 81
34 91
36 100
38 108
40 115
42 123
43 130
44 137
44 144
45 150
45 158
45 165
45 172
45 179
46 185
46 191
46 196
46 201
46 206
46 211
46 216
Min I (mA)
0
–5
–10
–15
–19
–23
–28
–31
–35
–38
–40
–44
–46
–48
–50
–51
–52
–52
–52
–53
–53
–53
–54
–54
–54
–54
–55
–55
Pull-Up
Max I (mA)
0
–15
–27
–38
–49
–60
–72
–83
–96
–104
–112
–120
–125
–130
–134
–137
–140
–143
–146
–149
–152
–154
–156
–157
–159
–160
–161
–162
Rev 1.0, November 21, 2006
Page 5 of 7
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| PDF Descargar | [ Datasheet CY2SSTV16857.PDF ] | |
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