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PDF ASM3P623S00A Data sheet ( Hoja de datos )
| Número de pieza | ASM3P623S00A | |
| Descripción | Zero Cycle Slip Peak EMI reduction IC | |
| Fabricantes | Alliance Semiconductor Corporation | |
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July 2005
wrewvw.D1a.0taSheet4U.com
ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI reduction IC
General Features
Input frequency range: 20MHz - 50MHz.
Zero input - output propagation delay.
Low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
Less than 200pS cycle-to-cycle jitter is compatible
with Pentium® based systems.
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S00A/B/C).
3.3V operation
Advanced 0.35µ CMOS technology.
The First True Drop-in Solution.
Functional Description
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out eight low-skew clocks. It is
available in a 16pin package. The ASM3P623S00A/B/C is
the eight-pin version of the ASM3P623S00. It accepts one
reference input and drives out one low-skew clock.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00D/E/F devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Please refer “Differential Cycle Slips and Spread Spectrum
Control Table” for deviations and differential Cycle Slips
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F
devices
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F
are available in two different configurations, as shown in
the ordering information table.
Block Diagram
VDD SSON SS%
CLKIN
Reference
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Feedforward
Divider
CLKOUT
VSS
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
July 2005
ASM3P623S00A/B/C/D/E/F
wrewvw.D1a.0taSheet4U.com
Operating Conditions for ASM3P623S00A/B/C and ASM3P623S00D/E/F Devices
Parameter
Description
VDD Supply Voltage
TA Operating Temperature (Ambient Temperature)
CL Load Capacitance
CIN Input Capacitance
Min Max Unit
3.0 3.6 V
0 70 °C
30 pF
7 pF
Electrical Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F
Parameter
Description
VIL Input LOW Voltage5
VIH Input HIGH Voltage5
IIL Input LOW Current
IIH Input HIGH Current
VOL Output LOW Voltage6
VOH Output HIGH Voltage6
IDD Supply Current
Zo Output Impedance
Test Conditions
VIN = 0V
VIN = VDD
IOL = 8mA
IOH = -8mA
Unloaded outputs
Min Typ Max Unit
0.8 V
2.0 V
50 µA
100 µA
0.4 V
2.4 V
15 mA
23 Ω
Switching Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F7
Parameter
Description
Test Conditions
Min
1/t1
t3
t4
t5
t6
t7
tJ
tLOCK
Output Frequency
Duty Cycle 6 = (t2 / t1) * 100
Output Rise Time 6
Output Fall Time 6
Output-to-output skew 6
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge 6
Device-to-Device Skew 6
Cycle-to-cycle jitter 6
PLL Lock Time 6
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at VDD /2
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
20
40
Notes:
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. All parameters specified with loaded outputs.
Typ
50
Max
50
60
2.5
2.5
250
Unit
MHz
%
nS
nS
pS
±350 pS
700 pS
200 pS
1.0 mS
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
5 of 16
5 Page 
July 2005
wrewvw.D1a.0taSheet4U.com
ASM3P623S00A/B/C/D/E/F
16-lead Thin Shrunk Small Outline Package (4.40-MM Body)
81
EH
PIN 1 ID
9 16 A
eB
D
A2 A1
Seating Plane
θ
L
C
Symbol
A
A1
A2
B
C
D
E
e
H
L
θ
Dimensions
Inches
Millimeters
Min Max Min Max
0.043
1.20
0.002
0.006
0.05
0.15
0.031
0.041
0.80
1.05
0.007
0.012
0.19
0.30
0.004
0.008
0.09
0.20
0.193
0.201
4.90
5.10
0.169
0.177
4.30
4.50
0.026 BSC
0.65 BSC
0.252 BSC
6.40 BSC
0.020
0.030
0.50
0.75
0° 8° 0° 8°
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
11 of 16
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ASM3P623S00A.PDF ] | |
Hoja de datos destacado
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| ASM3P623S00A | Zero Cycle Slip Peak EMI reduction IC | Alliance Semiconductor Corporation |
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| ASM3P623S00C | Zero Cycle Slip Peak EMI reduction IC | Alliance Semiconductor Corporation |
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