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PDF CYM1471 Data sheet ( Hoja de datos )
| Número de pieza | CYM1471 | |
| Descripción | (CYM1471 / CYM1481) 2048k X 8 SRAM Module | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CYM1471 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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fax id: 20061CYM1481
www.DataSheet4U.com
CYM1471
CYM1481
Features
• High-density 8-/16-megabit SRAM modules
• High-speed CMOS SRAMs
— Access time of 70 ns
• Low active power
— 605 mW (max.), 2M x 8
• Double-sided SMD technology
• TTL-compatible inputs and outputs
• Small footprint SIP
— PCB layout area of 0.72 sq. in.
• 2V data retention (L version)
Functional Description
The CYM1471 and CYM1481 are high-performance 8-mega-
bit and 16-megabit static RAM modules organized as 1024K
words (1471) or 2048K words (1481) by 8 bits. These modules
1024K x 8 SRAM Module
2048K x 8 SRAM Module
are constructed from eight (1471) or sixteen (1481) 128K x 8
SRAMs in plastic surface-mount packages on an epoxy lami-
nate board with pins. On-board decoding selects one of the
SRAMs from the high-order address lines, keeping the re-
maining devices in standby mode for minimum power con-
sumption.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When MS and WE inputs
are both LOW, data on the eight data input/output pins is writ-
ten into the memory location specified on the address pins.
Reading the device is accomplished by selecting the device
and enabling the outputs MS and OE active LOW while WE
remains inactive or HIGH. Under these conditions, the content
of the location addressed by the information on the address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the module is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
A0–A16
17
OE
WE
A17–A20
4
1 of 8
DECODER
MS
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
1 of 8
DECODER
128K x 8
SRAM
/
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
1471-1
Pin Configuration SIP
Top View
A19
VCC
WE
I/O2
I/O3
I/O0
CYM1471
A1
A2
A3
A4
GND
I/O5
A10
A20 (1481)
A11
A5
A13
A14
MS (1471)
MS
A15
A16
A12
A18
A6
I/O1
GND
A0
A7
A8
A9
I/O7
I/O4
I/O6
A17
8
I/O0–I/O7
VCC
OE
1471-2
1
2
3
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5
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8
9
10
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12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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31
32
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35
36
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1990 – Revised January 2, 1997
1 page  
:
www.DataSheet4U.com
Switching Waveforms (continued)
Read Cycle No. 2[8, 9]
MS
tAMS
OE
DATA OUT
tDOE
tLZOE
HIGH IMPEDANCE
tLZMS
tRC
CYM1471
CYM1481
DATA VALID
tHZOE
tHZMS
HIGH
IMPEDANCE
1471-8
Write Cycle No. 1[5, 10]
ADDRESS
MS
WE
DATA IN
DATA I/O
tWC
tSMS
tAW
tSA
DATA UNDEFINED
tPWE
tHA
tSD tHD
DATA VALID
tHZWE
tLZWE
HIGH IMPEDANCE
Notes:
9. WE is HIGH for read cycle.
10. Data I/O is high impedance if OE = VIH.
1471-9
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CYM1471.PDF ] | |
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