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PDF CY7C1379B Data sheet ( Hoja de datos )
| Número de pieza | CY7C1379B | |
| Descripción | 9-Mbit (256K x 32) Flow-through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1379B
9-Mbit (256K x 32) Flow-through SRAM
with NoBL™ Architecture
Features
Functional Description[1]
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.0 ns (for 117-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP and 165 fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
The CY7C1379B is a 3.3V, 256K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1379B is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
www.DataSheet4AU0.,cAo1m, A
CLK
CEN
MODE
C
CE
ADV/LD
BWA
BWB
BWC
BWD
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
READ LOGIC
SLEEP
Control
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05438 Rev. *A
Revised April 15, 2004
1 page  
CY7C1379B
CY7C1379B—Pin Definitions(continued)
Name
VSS
NC
VSS/DNU
TQFP
fBGA
5,10,17,21,
26,40,55,60,
67,71,76,90,
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
1,16,30,38,39, A1,A11,B1,
42,43,51,66,80, B9,B11,C1,
84,95,96 C2,C10,C11,
H1,H3,H9,
H10,N1,N2,
N5,N6,N7
N10,N11,P1,
P2,P5,P7,
P11,R2,R5,
R7
14 -
I/O
Ground
–
Ground/DNU
Description
Ground for the device.
No Connects. Not Internally connected to the die.
18M,36M,72M, 144M and 288M are address expansion pins and
are not internally connected to the die.
This pin can be connected to Ground or should be left floating.
Functional Overview
The CY7C1379B is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
www.Da(tCaSEh1e, eCt4EU2.,cComE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:D] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1379B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs.
Document #: 38-05438 Rev. *A
Page 5 of 15
5 Page 
Switching Waveforms
Read/Write Waveforms [18, 19, 20]
1 2 tCYC 3
CLK
tCENS tCENH
tCH tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BW[A:D]
ADDRESS A1
tAS tAH
A2
DQ
OE
COMMAND
D(A1)
tDS tDH
D(A2)
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
45678
A3
tCDV
tCLZ
D(A2+1)
A4 A5 A6
tDOH
tOEV tCHZ
Q(A3)
Q(A4)
Q(A4+1)
tOEHZ
tDOH
tOELZ
D(A5)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
CY7C1379B
9 10
A7
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
DON’T CARE
UNDEFINED
www.DataSheet4U.com
Notes:
18. For this waveform ZZ is tied LOW.
19. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05438 Rev. *A
Page 11 of 15
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1379B.PDF ] | |
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