PDF CY2SSTV8575 Data sheet ( Hoja de datos )

Número de pieza	CY2SSTV8575
Descripción	Differential Clock Buffer/Driver
Fabricantes	Cypress Semiconductor
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No Preview Available ! TV8575 Features • Operating frequency: 60 MHz to 170 MHz • Supports 266-MHz DDR SDRAM • 5 differential outputs from 1 differential input • Spread Spectrum compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power Management Control input • High-impedance outputs when input clock < 20 MHz • 2.5V operation • 32-pin TQFP JEDEC MS-026 C Block Diagram CY2SSTV8575 Differential Clock Buffer/Driver Description The CY2SSTV8575 is a high-performance, low-skew, low jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV8575 generates five differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV8575 features differential feedback clock outputs and inputs. This allows the CY2SSTV8575 to be used as a zero-delay buffer. When used as a zero-delay buffer in nested clock trees, the CY2SSTV8575 locks onto the input reference and translates with near zero delay to low-skew outputs. Pin Configuration OE 23 AVDD 8 Test and Powerdown Logic CLK 5 CLK# 6 FBIN 21 www.DataShFeB# Iet4U22 .com N PLL 2 Y0 1 Y0# 12 Y1 11 Y1# 15 Y2 16 Y2# 27 Y3 28 Y3# 30 Y4 31 Y4# 18 FBOUT 19 FBOUT# VSS VDDQ Y3 Y3# VDDQ Y4 Y4# VSS 24 23 22 21 20 19 18 17 CY2SSTV8575 TQFP-32 JEDEC MS-026 C 12345678 Y2# Y2 VSS VDDQ Y1 Y1# VSS AVSS Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07458 Rev. Revised October 30, 2002 1 page CY2SSTV8575 Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any volt- age higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD (VDDQ Voltage) Unused inputs must always be tied to an appropriate logic volt- age level (either VSS or VDDQ). Parameter Vdd VDD Vin Vout Ts Ta ØJc ØJa ESDh FIT Description Supply Voltage Operating Voltage Input Voltage Output Voltage Temperature, Storage Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Conditions Non Functional Functional Relative to VSS Relative to VSS Non Functional Functional Functional Functional Manufacturing test Min. –0.3 2.38 –0.3 –0.3 –65 0 – – – – Max. 3.5 2.63 2.63 2.63 150 +85 18 48 2K 10 Unit VDC VDC VDC VDC °C °C °C/W °C/W Volts ppm DC Parameters (AVDD = VDDO = 2.5 ±5%, Temperature = 0°C to +85°C) Parameter Description Conditions VIL Input Voltage, Low[3] VIH Input Voltage, High[3] OE VOL Output Voltage, Low VDDQ = 2.375V, IOL = 12 mA VOH Output Voltage, High VDDQ = 2.375V, IOH = –12 mA IOL Output Low Current VDDQ = 2.375V, VOUT = 1.2V IOH IDDQ Output High Current Dynamic Supply Current[4] VDDQ = 2.375V, VOUT = 1V ALL VDDQ, FO = 170 MHz w w w I.PDDSa t a S hPeoweetr D4 oUwn. Cc uorrment Cin Input pin capacitance OE = 0 or CLK/CLK# < 20 MHz Notes: 3. Unused inputs must be held high or low to prevent them from floating. 4. All outputs switching loaded with 16pF in 60Ω environment. See Figure 3. Min. – 1.75 – 1.7 26 28 – – – Typ. – – – – 35 –32 235 – – Max. 0.75 – 0.6 – – – 300 100 4 Unit V V V V mA mA mA. µA. pF Document #: 38-07458 Rev. Page 5 of 8 5 Page

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