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PDF WCMB2016R4X Data sheet ( Hoja de datos )
| Número de pieza | WCMB2016R4X | |
| Descripción | 128K x 16 Static RAM | |
| Fabricantes | Weida Semiconductor | |
| Logotipo |  |
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WCMB2016R4X
Features
• Low voltage range:
— 1.65V−1.95V
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 1.5 mA @ f = fmax
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMB2016R4X is a high-performance CMOS static
RAM organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This device is ideal for portable applications such as cellular
telephones. The device also has an automatic power-down
feature that significantly reduces power consumption by 99%
when addresses are not toggling. The device can also be put
into standby mode when deselected (CE HIGH or both BLE
Logic Block Diagram
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A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
2048 X 1024
128K x 16 Static RAM
and BHE are HIGH). The input/output pins (I/O0 through I/O15)
are placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The WCMB2016R4X is available in a 48-ball FBGA package.
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
1 page  
WCMB2016R4X
Switching Characteristics Over the Operating Range[8]
WCMB2016R4X
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC Read Cycle Time
70
ns
tAA Address to Data Valid
70 ns
tOHA
Data Hold from Address Change
10
ns
tACE CE LOW to Data Valid
70 ns
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 10]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 10]
35 ns
5 ns
25 ns
10 ns
25 ns
tPU CE LOW to Power-Up
0
ns
tPD CE HIGH to Power-Down
70 ns
tDBE
BLE / BHE LOW to Data Valid
tLZBE
BLE / BHE LOW to Low Z[9]
tHZBE
BLE / BHE HIGH to High Z[9, 10]
WRITE CYCLE[11]
5
70 ns
ns
25 ns
tWC Write Cycle Time
70
ns
tSCE CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tBW
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BLE / BHE LOW to Write End
Data Set-Up to Write End
60
30
ns
ns
tHD Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z[9, 10]
25 ns
tLZWE
WE HIGH to Low Z[9]
10
ns
Note:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and
output loading of the specified IOL/IOH and 30 pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than
tLZWE for any given device.
10. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high impedence state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be
referenced to the edge of the signal that terminates the write.
5
5 Page 
WCMB2016R4X
Document Title: WCMB2016R4X, 128K x 16 Static RAM
REV.
Spec #
ECN #
Issue Date
** 38-14011
115226
4/24/2002
Orig. of Change Description of Change
MGN
New Data Sheet
.
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet WCMB2016R4X.PDF ] | |
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