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PDF HT46R01N Data sheet ( Hoja de datos )
| Número de pieza | HT46R01N | |
| Descripción | (HT4xR0xx) Small Package 8-Bit OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Small Package 8-Bit OTP MCU
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features
· Operating voltage:
fSYS= 4MHz: 2.2V~5.5V
fSYS= 8MHz: 3.0V~5.5V
fSYS= 12MHz: 4.5V~5.5V
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD= 5V
· Sleep mode and wake-up functions to reduce
power consumption
· Oscillator types:
External high freuency Crystal -- HXT
External RC -- ERC
Internal RC -- HIRC
External low frequency crystal -- LXT
· Three operational modes: Normal, Slow, Sleep
· Fully integrated internal 4MHz, 8MHz and 12MHz
oscillator requires no external components
· OTP Program Memory: 1K´15 ~ 2K´15
· RAM Data Memory: 96´8
· Watchdog Timer function
· LIRC oscillator function for watchdog timer
· All instructions executed in one or two instruction
cycles
· Table read instructions
· 63 powerful instructions
· 6-level subroutine nesting
· Bit manipulation instruction
· Low voltage reset function
· 10-pin MSOP, 16-pin NSOP package types
Peripheral Features
· Up to 10 bidirectional I/O lines
· 4 channel 12-bit ADC
· 1 channel 8-bit PWM
· External interrupt input shared with an I/O line
· Two 8-bit programmable Timer/Event
Counter with overflow interrupt and prescaler
· Time-Base function
· Programmable Frequency Divider - PFD
General Description
The Small Package MCUs are a series of 8-bit high per-
formance, RISC architecture microcontrollers specifi-
www.DataSheet4Uca.clloymdesigned for a wide range of applications. The
usual Holtek microcontroller features of low power con-
sumption, I/O flexibility, timer functions, oscillator op-
tions, power down and wake-up functions, watchdog
timer and low voltage reset, combine to provide devices
with a huge range of functional options while still main-
taining a high level of cost effectiveness. The fully inte-
grated system oscillator HIRC, which requires no
external components and which has three frequency
selections, opens up a huge range of new application
possibilities for these devices, some of which may in-
clude industrial control, consumer products, household
appliances subsystem controllers, etc.
Rev.1.00
1 December 15, 2009
1 page  
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
Note:
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
The important point to note here is that the PB0 and PB1 pads will not be bounded to pins in the 10-pin MSOP
package. These two pads default to an input state, the designer should set the register PBPU to pull high op-
tions. In this way, these two internal pads can be pulled up in order to prevent input pin floating power con-
sumption.
HT46R01N/HT46R02N
Pin Name Function OPT I/T O/T
Description
PA0/AN0
PA0
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
AN0 ADCR AN
¾ A/D channel 0
PA1/PFD/AN1
PA1
PFD
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CTRL0 ¾ CMOS PFD output
PA2/TC0/AN2
PA3/INT/AN3
AN1 ADCR AN
¾ A/D channel 1
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0 ¾ ST ¾ External Timer 0 clock input
AN2 ADCR AN
¾ A/D channel 2
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
INT ¾ ST ¾ External interrupt input
PA4/TC1/PWM
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PA5/OSC2
PA6/OSC1
PA7/RES
PB0
PB1
AN3
PA4
TC1
PWM
PA5
OSC2
PA6
OSC1
PA7
RES
PB0
PB1
ADCR AN
¾ A/D channel 3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾ ST ¾ External Timer 1 clock input
CTRL0 ¾ CMOS PWM output
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CO ¾ OSC Oscillator pin
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CO OSC ¾ Oscillator pin
PAWK ST NMOS General purpose I/O. Register enabled wake-up.
CO ST
¾ Reset input
PBPU ST CMOS General purpose I/O. Register enabled.
PBPU ST CMOS General purpose I/O. Register enabled.
VDD
VSS
VDD
VSS
¾ PWR ¾ Power supply
¾ PWR ¾ Ground
Rev.1.00
5 December 15, 2009
5 Page 
HT46R01B/02B/01N/02N
HT48R01B/02B/01N/02N
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the inter-
nal system architecture. The range of devices take ad-
vantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It car-
ries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The inter-
nal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two instruction cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
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O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m C o u n te r
PC
PC +1
PC +2
P ip e lin in g
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 M O V A ,[1 2 H ]
2 C A LL D E LA Y
3 C P L [1 2 H ]
4:
5:
6 D E LA Y : N O P
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
Rev.1.00
11 December 15, 2009
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT46R01N.PDF ] | |
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