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PDF AS7C1025B Data sheet ( Hoja de datos )

Número de pieza AS7C1025B
Descripción 5V 128K X 8 CMOS SRAM
Fabricantes Alliance Semiconductor Corporation 
Logotipo Alliance Semiconductor Corporation Logotipo



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No Preview Available ! AS7C1025B Hoja de datos, Descripción, Manual

March 2004
AS7C1025B
www.DataSheet4U.com
®
5V 128K X 8 CMOS SRAM (Center power and ground)
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 605mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
Logic block diagram
VCC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
Input buffer
512 x 256 x 8
Array
(1,048,576)
I/O7
I/O0
Column decoder
Control
circuit
WE
OE
CE
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• ESD protection 2000 volts
• Latch-up current 200 mA
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24 VCC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
-10
10
5
110
10
-12 -15
12 15
67
100 90
10 10
-20 Unit
20 ns
8 ns
80 mA
10 mA
3/26/04, v. 1.3
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.

1 page




AS7C1025B pdf
AS7C1025B
www.DataSheet4U.com
®
Write cycle (over the operating range)11
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Symbol
tWC
tCW
tAW
tAS
tWP
tWR
tAH
tDW
tDH
tWZ
tOW
-10 -12 -15 -20
Min Max Min Max Min Max Min Max
10 - 12 – 15 – 20 –
8 - 9 – 10 – 12 –
8 - 9 – 10 – 10 –
0 - 0–0 – 0 –
7 - 8 – 9 – 12 –
0 - 0–0 – 0 –
0 - 0–0 – 0 –
5 - 6 – 8 – 10 –
0 - 0–0 – 0 –
- 5 –6– 7 – 8
1 - 1–1 – 2 –
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4, 5
4, 5
4, 5
Write waveform 1 (WE controlled)10,11
tWC
tAW
Address
WE
tAS
tWP
DIN
tWZ
DOUT
tWR
tAH
tDW
Data valid
tOW
tDH
3/26/04, v. 1.3
Alliance Semiconductor
P. 5 of 9

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