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LC78628 PDF даташит

Спецификация LC78628 изготовлена ​​​​«Sanyo Semicon Device» и имеет функцию, называемую «Compact Disc Player DSP with Built-in HDCD Decoder».

Детали детали

Номер произв LC78628
Описание Compact Disc Player DSP with Built-in HDCD Decoder
Производители Sanyo Semicon Device
логотип Sanyo Semicon Device логотип 

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LC78628 Даташит, Описание, Даташиты
Ordering number : ENN6329
CMOS IC
LC78628E
Compact Disc Player DSP with Built-in HDCD Decoder
®
Overview
The LC78628E CMOS IC implements signal processing
and servo control for compact disc players, laser disc
players, CD-V, CD-I, and similar products. It provides
functions for demodulation of the EFM signal from the
optical pickup, deinterleaving, error detection and
correction, and processing servo system commands issued
by the system microprocessor. In addition to this basic CD
functionality, it also provides HDCD (High Definition
Compatible Digital) decoding functions and CD text
functions. It also includes a built-in EFM PLL circuit.
Functions
• Full decoding and playback for discs encoded with the
HDCD technique developed by Pacific Microsonics,
Inc.
• Slices the high-frequency input signal at an accurate
level, converts it into the EFM signal, and generates a
PLL clock with an average frequency of 4.3218 MHz
performing a phase comparison with an internal VCO.
• Accurately generates a reference clock signal and all
necessary internal timings using an external 16.9344-
MHz crystal.
• Controls the disc motor speed using a frame phase
difference signal created based on the reproduced clock
signal and the reference clock.
• Performs detection, protection, and interpolation for the
frame synchronizing signal to assure stable data readout.
• Demodulates the EFM signal, converting it to 8-bit
symbol data.
• After applying a CRC check to the subcode Q signal,
outputs that data to the control microprocessor using
serial data transfer.
Package Dimensions
Continued on next page.
unit: mm
3174-QIP80E
0.8 0.8
64
65
[LC78628E]
23.2
20.0
0.35
1.6
41
40
0.15
80
1
25
24
2.7
21.6 0.8
SANYO: QIP80E
®
HDCD® (High Definition Compatible Digital®) is a registered trademark of Pacific Microsonics, Inc.
in the US and other countries.
A license from Pacific Microsonics, Inc. is required to use this product.
Sanyo Electric Co., Ltd. has acquired license for the use of HDCD technology from Pacific Microsonics, Inc.
The following patents apply to the design of this product:
USA: 5479168, 5638074, 5640161, 5808574, 5838274, 5854600, and 5872531.
Australia: 669114
Other patents have also been applied for.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32400RM (OT) No. 6329-1/40









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LC78628 Даташит, Описание, Даташиты
LC78628E
Continued from preceding page.
• Buffers the demodulated EFM signal data in internal
RAM and compensates for ±4 frames of jitter due to
disc speed fluctuations.
• Performs unscrambling and deinterleaving by reordering
the demodulated EFM signal data to the stipulated order.
• Performs error detection and correction and flag
processing (C1: dual errors, C2: dual errors)
• The C2 flags are set based on the C1 flags and the result
of the C2 processing, and the signal is interpolated or
muted according to the C2 flags. Four-sample
interpolation is adopted in the interpolation circuit.
Linear (average value) interpolation is applied if up to
three consecutive errors are indicated by the C2 flags,
and muting at the zero level is applied if four or more
consecutive errors are indicated.
• Performs track jump, focus start, disc motor start/stop,
muting on/off, track count, and other operations by
executing 8- or 16-bit commands serially input from the
system microprocessor.
• Supports high-speed disc access operations based on
arbitrary track counts.
• Provides digital outputs.
• Built-in Σ∆ D/A converter based on a third-order noise
shaper.
• Zero-cross muting
• Digital attenuator and deemphasis filter
• Support 2 × speed playback
• Bilingual function
• Built-in text decoder
• Five general-purpose I/O ports
Features
• 80-pin QFP package
• Fabricated in a silicon gate CMOS process
• 3.3 and 5 V power supply voltages
Block Diagram
DEFI
EFMIN
FSEQ
CLV+
CLV–
V/P
TEST6
CS
WRQ
SQOUT
CQCK
COIN
RWC
Slice level
control
Synchronization
EFM demodulation
CLV
digital servo
Subcode
separation
Q CRC
Microprocessor
interface
Servo
commander
VCO
clock control
2k × 8bits
RAM
C1 and C2 error
detection and correction
flag processing
Text
decoder
I/O ports
Crystal oscillator
System timing generator
RAM address
generator
Interpolation
mute
Bilingual
MUX, S–P
HDCD
decoder
MUX
8·Fs HDCD
interpolation
filter
De-emphasis
attenuator
1-bit DAC
LRSY
C2F
ROMXA
LRCKI
BCKI
DATAI
Digital
output
DOUT
GAIN
HDCD
M
U
DFOLO
DACKO
X LRCKO
DFORO
A12795
No. 6329-2/40









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LC78628 Даташит, Описание, Даташиты
Pin Assignment
LC78628E
SQOUT
COIN
CQCK
RES
TST11
SCLK
DQSY
4.2M
SRDT
TEST5
CS
LRSY
CK2
ROMXA
C2F
TEST1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
LC78628E
40 P2
39 P1
38 P0
37 GAIN
36 DACKO
35 DFOLO
34 DFORO
33 LRCKO
32 EMPH
31 TEST4
30 16M
29 JP–
28 JP+
27 VDD3V
26 TEST3
25 HDCD
A12796
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
Conditions
VDD max1
VDD max2
VIN5 max
VIN3 max
VOUT5 max
VOUT3 max
Pd max
VDD, VVDD, XVDD, LVDD, RVDD
VDD3V
Topr
Tstg
Ratings
VSS – 0.3 to VSS + 6.0
VSS – 0.3 to VSS + 4.0
VSS – 0.3 to VDD1 + 0.3
VSS – 0.3 to VDD2 + 0.3
VSS – 0.3 to VDD1 + 0.3
VSS – 0.3 to VDD2 + 0.3
500
–20 to +75
–40 to +125
Unit
V
V
V
V
V
V
mW
°C
°C
Allowable Operating Conditions at Ta = 25°C, VSS = 0 V
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Symbol
VDD1
VDD2
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
Conditions
VDD, VVDD, XVDD, LVDD, RVDD
VDD3V
DEFI, COIN, RES, HFL, TES, RWC, CQCK, TAI, SCLK,
CS, PCCL, LRCKI, BCKI, DATAI
P0 to P4, TEST1 to TEST5, EMPH
EFMIN
DEFI, COIN, RES, HFL, TES, RWC, CQCK, TAI, SCLK,
CS, PCCL, LRCKI, BCKI, DATAI
P0 to P4, TEST1 to TEST5, EMPH
EFMIN
min
4.5
3.0
0.8 VDD1
0.7 VDD1
0.6 VDD1
0
0
0
Ratings
typ
5.0
3.3
max
5.5
3.6
Unit
V
V
VDD1
V
VDD1
VDD1
V
V
0.2 VDD1
V
0.3 VDD1
V
0.4 VDD1
V
Continued on next page.
No. 6329-3/40










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