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LC80101M PDF даташит

Спецификация LC80101M изготовлена ​​​​«Sanyo Semicon Device» и имеет функцию, называемую «VICS LSI».

Детали детали

Номер произв LC80101M
Описание VICS LSI
Производители Sanyo Semicon Device
логотип Sanyo Semicon Device логотип 

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LC80101M Даташит, Описание, Даташиты
Ordering number : EN54384465
CMOS LSI
LC80101M
VICS LSI
Overview
The LC80101M is a special-purpose descrambler LSI for
use in VICS systems. FM multiplexed service data that
has had VICS center scrambling applied can be
descrambled and received by inserting this LSI in the
serial interface between the LC72700E and the application
CPU. This architecture also supports reception of regular
transmissions that have not been scrambled. Note that
sample evaluation and product manufacture using this LSI
require a contract with the VICS Center organization.
Functions
• VICS scrambled/unscrambled recognition circuit
• Dedicated VICS descrambler circuit
• CPU interface circuit (CCB: serial)
Package Dimensions
unit: mm
3091A-MFP28
[LC80101M]
SANYO: MFP28
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Input voltage
Output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
VIN1
VIN2
VOUT1
VOUT2
Pdmax
Topr
Tstg
Conditions
Ratings
VDD
The CL2, CE2, DI2, RST2, BACKUP, INT-R1, and DI1 pins
–0.3 to +7.0
–0.3 to +7.0
Input pins other than VIN1
The DO2 pin
–0.3 to VDD +0.3
–0.3 to +7.0
Output pins other than VOUT1
Ta 85°C
–0.3 to VDD +0.3
200
–40 to +85
–55 to +125
Unit
V
V
V
V
V
mW
°C
°C
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
53096HA (OT) No. 5438-1/9









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LC80101M Даташит, Описание, Даташиты
LC80101M
Serial Input and Output (See the serial data timing figures.)
Parameter
Clock low-level time
Clock high-level time
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
Data output time
Symbol
Conditions
tCL CL2
tCH CL2
tSU CL2, DI2
tHD CL2, DI2
tEL CL2, CE2
tES CL2, CE2
tEH CL2, CE2
tDH DO2: Varies with the value of the pull-up resistor used
min
0.7
0.7
0.7
0.7
0.7
0.7
0.7
Ratings
typ
max
1
Unit
µs
µs
µs
µs
µs
µs
µs
µs
Electrical Characteristics/Input and Output Levels at Ta = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min typ max
Input high-level voltage
Input low-level voltage
VIH CMOS-compatible Schmitt inputs
Pull-down resistors: INT-R1, TEST1 to TEST4,
VIL and TESTON
0.8 VDD
0.2 VDD
V
V
Input high-level voltage
Input low-level voltage
Output high-level voltage
Output low-level voltage
Output low-level voltage
Standby current
VIH CMOS-compatible Schmitt inputs:
VIL BACKUP, CE2, CL2, DI1, DI2, and RST2
VOH IOH = –4 mA: CE1, CL1, DO1, INT-R2
VOL IOL = 4 mA: CE1, CL1, DO1, INT-R2
VOL IOL = 2 mA: DO2
Isd With the BACKUP pin low
0.8 VDD
VDD – 2.1
0.2 VDD
0.01
0.4
0.4
10
V
V
V
V
V
µA
Input sensitivity
Pull-down resistance
Vck Rf = 1 M, FILCK1 = 3.6 MHz: FILCK1*1
Rd INT-R1, TEST1 to 4, TESTON
1.0 VDD Vp-p
70 140 280 k
Current drain
IDD1
IDD2
IDD3
IDD4
Sine wave input: 1 V p-p, VDD = 5.0 V*2
Sine wave input: 5 V p-p, VDD = 5.0 V*2
Square wave input: 1 V p-p, VDD = 5.0 V*2
Square wave input: 5 V p-p, VDD = 5.0 V*2
6 15 mA
2.5 7 mA
5 13 mA
1.5 4 mA
Note 1. Since this LSI operates based on the rising edge of the LC72700E 3.6 MHz output (the FILCK pin), the LC72700E 3.6 MHz output signal must be
input to the FILCK1 pin without inverting the polarity.
2. The current drain varies with the input level and the shape of the clock signal input to the FILCK1 pin. The current drain can be reduced by using
waveforms that are closer to square waves than to sine waves, and by using a signal level that is close to VDD. The LC72700E 3.6 MHz output is a
square wave with an output level equal to VDD.
Block Diagram
No. 5438-2/9









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LC80101M Даташит, Описание, Даташиты
LC80101M
Pin Assignments and Functions
Pin No.
Pin
Function overview
TEST1
Test pin 1 (Must be connected to ground or left open in normal operation.)
1
TEST2
Test pin 2 (Must be connected to ground or left open in normal operation.)
9
TEST3
Test pin 3 (Must be connected to ground or left open in normal operation.)
19
TEST4
Test pin 4 (Must be connected to ground or left open in normal operation.)
27
TESTON
Test pin (Must be connected to ground in normal operation.)
13
Rd: Input pin internal pull-down resistor
5 DI1 Inputs the output of the LC72700E pin 32. An external pull-down resistor is
required. See the following page.
20
BACKUP
Input that selects normal operation when high and backup mode when low.
Clock input for the CCB serial interface
21 CL2
22
CE2
Control input for the CCB serial interface
23 DI2 Data input for the CCB serial interface
26
RST2
System reset input (negative logic)
4
INT-R1
Inputs the output of the LC72700E pin 35.
Rd: Input pin internal pull-down resistor
Input or output circuit type
6
DO1
Output to the LC72700E pin 31 input
7
CE1
Output to the LC72700E pin 30 input
8 CL1 Output to the LC72700E pin 29 input
25
INT-R2
Outputs an output data interrupt to the external CPU
24
DO2
Data output for the CCB serial interface
2
FILCK1
System clock generator input
3
FICLK2
System clock generator output
Rf: External feedback resistor, 510 kto 1.5 M(typical: 1 M)
28
14
10, 11,
12, 15,
16, 17
18
VDD Power supply (+4.5 to 5.5 V)
VSS Ground connection
NC No connection pins. These pins must be left open.
No. 5438-3/9










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