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LC8213K PDF даташит

Спецификация LC8213K изготовлена ​​​​«Sanyo Semicon Device» и имеет функцию, называемую «Image Data Compression/Expansion Processor».

Детали детали

Номер произв LC8213K
Описание Image Data Compression/Expansion Processor
Производители Sanyo Semicon Device
логотип Sanyo Semicon Device логотип 

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LC8213K Даташит, Описание, Даташиты
Ordering number : EN *5753
CMOS LSI
LC8213K
Image Data Compression/Expansion Processor
Preliminary
Overview
The LC8213K compresses and expands the binary image
data used in fax and similar applications and can be used
in office automation equipment such as G3 or G4
facsimile systems, image filing systems, digital copiers,
and engineering workstations. The LC8213K supports
encoding methods that conform to the MH (Modified
Huffman), MR (Modified relative element address
designate), and MMR (Modified MR) encoding
techniques as stipulated in the ITU-T T.4 and T.6
recommendations.
Features
• Conforms to the ITU-T T.4 and T.6 MH, MR, and
MMR encoding methods.
• Supports G3 and G4 facsimile.
• Handles up to 64k bits in the main scan direction.
• Line skip mode
• 8/16-bit image memory bus, 8-bit CPU bus
• Supports data transfers between the CPU bus and the
image memory bus.
• DMA transfer function for data transfers between image
memory and I/O devices
• Executes encoding processing and DMA transfers
simultaneously
• System clock frequency: Up to 25 MHz
• CMOS structure supporting low power dissipation
Package Dimensions
unit: mm
3174-QFP80E
[LC8213K]
SANYO: QIP80E
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input and output voltages
Allowable power dissipation
Operating temperature
Storage temperature
Soldering conditions
Symbol
VDD max
VI, VO
Pd max
Topr
Tstg
Condition
Ta 70°C
Hand soldering: 3 seconds
Reflow soldering: 10 seconds
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
500
–30 to +70
–55 to +125
350
235
Unit
V
V
mW
°C
°C
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
93097HA (OT) No. 5753-1/5









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LC8213K Даташит, Описание, Даташиты
LC8213K
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V
Parameter
Supply voltage
Input voltage range
Symbol
VDD
VIN
Conditions
DC Characteristics at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V
Parameter
Input high-level voltage
Input low-level voltage
Input leakage current
Output high-level voltage
Output low-level voltage
Output leakage current
Input clock frequency
Current drain
Block Diagram
Symbol
Conditions
VIH1
VIL1
IL
VOH
VOL
IOZ
fCLK
IDD
IOH = –4 mA
IOL = 4 mA
For pins in the high-impedance output state
CLK
min
4.5
0
Ratings
typ
5.0
max
5.5
VDD
Unit
V
V
min
2.2
Ratings
typ
–10
2.4
–10
10
max
0.8
+10
0.4
+10
25
20
Unit
V
V
µA
V
V
µA
MHz
mA
A2 to A0
D7 to D0
MA23 to MA16
MA/MD15 to MA/MD0
TEST4 to TEST0
• CPU interface
This circuit is a general-purpose 8-bit CPU interface. The operating mode and other aspects are set by accessing the
interface registers and the parameter registers.
• Sequence controller
Controls the functional blocks in the IC according to the encoding or decoding algorithm being used.
• Encoder
Generates the codes in the various modes by recognizing inflection points in the image data. Encoded data is passed to
the data bus through an 8-bit 4-word encoding FIFO (EFIFO).
• Decoder
Recognizes the codes in the various modes and recovers the original image data. Image data is passed to the data bus
through a decoding FIFO (DFIFO).
• Image bus interface
Controls reads from and writes to image memory as well as DMA transfers on the image memory bus.
No. 5753-2/5









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LC8213K Даташит, Описание, Даташиты
LC8213K
Switching Characteristics at VDD = 2.7 to 5.5 V, Ta = –20 to +75°C, VSS = 0 V
I: Input pin O: Output pin B: Bi-directional pin P: Power supply pin NC: No connection
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin name
CS
RD
WR
A2
A1
A0
VDD
D7
D6
D5
D4
VSS
D3
D2
D1
D0
VDD
IREQ
DREQ
DACK
RESET
CLK
VSS
TEST4
VDD
TEST3
TEST2
TEST1
TEST0
BREQ
BACK
IDREQ
IDACK
AEN
AST
MDEN
MRD
MWR
IORD
IOWR
LDE
UDE
READY
I/O Function
I Chip select signal
I Read signal from the CPU
I Write signal from the CPU
I
I Address inputs
I
P Power supply
NC
B
B
Data bus
B
B
P Ground
B
B
Data bus
B
B
NC
P Power supply
O Interrupt request signal
O DMA request signal output to external DMA controller
I DMA acknowledge signal input from external DMA controller
NC
NC
NC
NC
I Reset signal input
I Clock input
P Ground
I Test pin
P Power supply
I
I
Test pin
I
I
NC
O Bus request signal for the image bus
I Acknowledge signal for the image bus
I DMA request signal from I/O devices
O DMA acknowledge signal to I/O devices
O Address enable
O Address strobe
O Memory data enable
O Image memory read signal
O Image memory write signal
O I/O device read signal
O I/O device write signal
O Image bus lower byte valid signal
O Image bus upper byte valid signal
I Ready signal
Continued on next page.
No. 5753-3/5










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Номер в каталогеОписаниеПроизводители
LC8213Image Data Compression/Expansion ProcessorSanyo Semicon Device
Sanyo Semicon Device
LC8213KImage Data Compression/Expansion ProcessorSanyo Semicon Device
Sanyo Semicon Device

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