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PDF AK7740ET Data sheet ( Hoja de datos )
| Número de pieza | AK7740ET | |
| Descripción | 24bit 2ch ADC + 24bit 4ch DAC | |
| Fabricantes | AKM Semiconductor | |
| Logotipo |  |
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[ASAHI KASEI]
[AK7740ET]
AK7740ET
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
1. General Description
The AK7740 is a highly integrated audio processing IC, including four 24-bit output D/A channels, a stereo 24-bit
input A/D, and an audio DSP. High quality analog output performance is provided by the quad DAC with 97dB
dynamic range, and the stereo ADC with 98dB dynamic range. The converters support sampling frequencies from
32kHz to 48kHz. This device includes 72kbits of SRAM audio delay that is suitable for simulated sound fields. The
DSP is optimized for audio signal processing. The design allows up to 512 execution lines per audio sample cycle,
with multiple functions per line. The AK7740 is ideal for sound field control applications, including echo, 3D,
parametric equalization, and speaker compensation. It is housed in a 48-lead LQFP package.
2. Features
www.DaDtaSSPh:eet4U.com
- Word length:
24-bit (Data RAM)
- Instruction cycle time: 40ns (512fs, fs=48kHz )
- Multiplier: 24 x 16 → 40-bit
- Divider: 24 / 24 → 16-bit or 24-bit
- ALU:
34-bit arithmetic operation (overflow margin: 4-bits)
- 24-bit arithmetic and logic operation
- Shift+Register: 1, 2, 3, 4, 6, 8 and 15 bits shifted left
- 1, 2, 3, 4, 8 , 14 and 15 bits shifted right
- Other numbers in parentheses are restricted. Provided with indirect shift function
- Program RAM:
- Coefficient RAM:
512 x 32-bit
512 x 16-bit
- Data RAM:
- Offset RAM:
256 x 24-bit
48 x 13-bit
- (6144 x 12-bit / 3072 x 24-bit / 4096 x 12-bit + 1024 x 24-bit )
- Internal Memory: 72kbit SRAM
- Sampling frequency: 32kHz to 48kHz
- Serial interface port for micro-controller
- Master clock: 512fs
- Master/Slave operation
- Serial signal input port ( 2 to 4 ch ): 16/20/24-bit : Output port ( 2 ch ): 24-bit
ADC: 2 channels
- 24-bit 64x over-sampling delta sigma
- DR, S/N : 98dBA ( full-differential Input )
- S/(N+D) : 89dB
- Digital HPF (fc = 1Hz)
- Single-ended or full-differential Input
DAC: 4 channels
- 24-bit 128x over-sampling advanced multi-bit
- DR, S/N : 97dBA
- S/(N+D) : 89dB
- Single ended or differential output
Input Selector
- 1 full-differential and 4 single-ended Input
Other
- Power supply: +3.3V±10%
- Operating temperature range: -10°C~70°C
- Package: 48pin LQFP (0.5mm pitch)
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2006/10
1 page  
[ASAHI KASEI]
[AK7740ET]
(2) Pin function
Pin No.
1
2
3
4
5
6
Pin name
AINL3
AINR2
AINL2
AINR1
AINL1
VREFH
7 AVDD
8 AVSS
9 DVSS
www.Da1t0aSheet4U.DcoVmDD
11 XTI
12 XTO
13 CLKO
14 JX
15 SMODE
16 LRCLK
17 BITCLK
18 SDIN
19 SDINA
I/O Function
I ADC single-ended analog Lch input pin 3
I ADC single-ended analog Rch input pin 2
I ADC single-ended analog Lch input pin 2
I ADC single-ended analog Rch input pin 1
I ADC single-ended analog Lch input pin 1
I Analog reference voltage input
Connect to AVDD (pin 7), and bypass with 0.1uF and
10uF capacitors between this pin and AVSS.
- Analog power supply 3.3V typical
- Analog ground
- Digital ground
- Digital power supply 3.3V typical
Master clock input
I Connect a crystal oscillator between this pin and the XTO pin,
or input an external CMOS clock signal to the XTI pin.
Crystal oscillator output
O When a crystal oscillator is used, connect between XTI and XTO.
When an external clock is used, keep this pin open
Clock output
O Outputs the XTI clock.
Allows the output to be set to "L" by control register setting.
I External condition jump (pulldown)
Slave/master mode selector
I Sets LRCLK and BITCLK to input or output mode.
SMODE="L": Slave mode (clock input mode)
SMODE="H": Master mode (clock output mode)
LR channel select clock
I/O SMODE="L": Slave mode: Inputs the fs clock
SMODE="H": Master mode: Outputs the fs clock
Serial bit clock
I/O SMODE="L": Slave mode: Inputs 64 fs or 48 fs clocks
SMODE="H": Master mode: Outputs 64 fs clocks
DSP serial data input ( Pulldown)
I Compatible with MSB/LSB justified 24, 20 and 16 bits.
DSP serial data input (Pulldown)
I When using the ADC, leave open or connect to DVSS.
Compatible with MSB justified 24 bits.
Classification
Analog section
Analog
Power Supply
Digital
Power Supply
System clock
System clock
Condition input
Control
System clock
Digital section
Serial input data
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5 Page 
[ASAHI KASEI]
[AK7740ET]
(5) Switching characteristics
5-1) System clock
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
Min
Master clock (XTI)
a) With crystal oscillator
384fs: frequency
512fs: frequency
b) With external clock:
Duty factor (≤18.432MHz)
(>18.432MHz)
:Frequency
: High level width
: Low level width
Clock rise time
Clock fall time
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LRCLK sampling frequency
fMCLK
fMCLK
fMCLK
tMCLKH
tMCLKL
tCR
tCF
fs
12.288
16.384
40
45
10.0
16
16
32
Slave mode :clock rise time
Slave mode :clock fall time
tLR
tLF
BITCLK
Note 1) fBCLK
Slave mode: High level width
tBCLKH
Slave mode: Low level width
tBCLKL
Slave mode :clock rise time
tBR
Slave mode :clock fall time
tBF
Note 1) 48fs mode can only be applied in slave mode.
48
150
150
5-2) Reset
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
INIT_RESET
Note 1)
Symbol
tRST
S_RESET
tRST
min
150
150
Typ
18.432
24.576
50
50
24.576
48
1
64
typ
Max Unit
19 MHz
25 MHz
60 %
55
25 MHz
ns
ns
6 ns
6 ns
50 kHz
fs
6 ns
6 ns
fs
ns
ns
6 ns
6 ns
max Unit
ns
ns
Note 1) “L” is acceptable when power is turned on, but ”H” requires a stable master clock input.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK7740ET.PDF ] | |
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