PDF CY7C1529AV18 Data sheet ( Hoja de datos )

Número de pieza	CY7C1529AV18
Descripción	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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CY7C1522AV18, CY7C1529AV18 CY7C1523AV18, CY7C1524AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description ■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self-timed writes ■ DDR-II operates with 1.5 cycle read latency when the DLL is enabled ■ Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode ■ 1.8V core power supply with HSTL inputs and outputs ■ Variable drive HSTL output buffers ■ Expanded HSTL output voltage (1.4V–VDD) ■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ JTAG 1149.1 compatible test access port ■ Delay Lock Loop (DLL) for accurate data placement Configurations The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1522AV18, two 9-bit words in the case of CY7C1529AV18, two 18-bit words in the case of CY7C1523AV18, and two 36-bit words in the case of CY7C1524AV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. CY7C1522AV18 – 8M x 8 CY7C1529AV18 – 8M x 9 CY7C1523AV18 – 4M x 18 CY7C1524AV18 – 2M x 36 Selection Guide Description Maximum Operating Frequency Maximum Operating Current www.DataSheet4U.com 300 MHz 300 x8 900 x9 900 x18 950 x36 1080 278 MHz 278 855 855 880 1000 250 MHz 250 800 800 800 900 200 MHz 200 700 700 700 750 167 MHz 167 650 650 650 650 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court Document #: 001-06981 Rev. C • San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2007 [+] Feedback 1 page CY7C1522AV18, CY7C1529AV18 CY7C1523AV18, CY7C1524AV18 Pin Configuration (continued) The pin configuration for CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1523AV18 (4M x 18) 1 2 3 4 5 6 7 8 9 10 A CQ NC/144M A R/W BWS1 K NC/288M LD A A B NC Q9 D9 A NC K BWS0 A NC NC C NC NC D10 VSS A A A VSS NC Q7 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC M NC NC D16 VSS VSS VSS VSS VSS NC Q1 N NC D17 Q16 VSS A A A VSS NC NC P NC NC Q17 A A C A A NC D0 R TDO TCK A A A C A A A TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI 12 A CQ NC/288M B Q27 Q18 C D27 Q28 D D28 D20 E Q29 D29 F Q30 Q21 G D30 D22 H DOFF VREF J D31 Q31 K Q32 D32 L Q33 Q24 M D33 Q34 www.DaNtaSheet4UD.c3o4m P Q35 D26 D35 R TDO TCK 3 A D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A CY7C1524AV18 (2M x 36) 4567 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A AACA 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Document #: 001-06981 Rev. C Page 5 of 30 [+] Feedback 5 Page CY7C1522AV18, CY7C1529AV18 CY7C1523AV18, CY7C1524AV18 Write Cycle Descriptions The write cycle description table for CY7C1529AV18 follows. [2, 8] BWS0 L L H K L–H – L–H K – During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device. L–H During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device. – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1524AV18 follows. [2, 8] BWS0 BWS1 BWS2 BWS3 K L L L L L–H K Comments – During the Data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L–H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L H H H L–H – During the Data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L H H H – L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. H L H H L–H – During the Data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. H L H H – L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. H H L H L–H – During the Data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. H H L H – L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. H H H L L–H – During the Data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. H H H L – L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. H H H H L–H – No data is written into the device during this portion of a write operation. H H H H – L–H No data is written into the device during this portion of a write operation. www.DataSheet4U.com Document #: 001-06981 Rev. *C Page 11 of 30 [+] Feedback 11 Page

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