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PDF CY62147EV18 Data sheet ( Hoja de datos )
| Número de pieza | CY62147EV18 | |
| Descripción | 4-Mbit (256K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY62147EV18 MoBL®
4-Mbit (256K x 16) Static RAM
Features
■ Very high speed: 55 ns
■ Wide voltage range: 1.65 V to 2.25 V
■ Pin compatible with CY62147DV18
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Ultra low standby power
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in a Pb-free 48-ball very fine ball grid array (VFBGA)
package
Functional Description
The CY62147EV18 is a high performance CMOS static RAM
organized as 256 K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (I/O0 through I/O15) are placed
in a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), both the Byte High
Enable and the Byte Low Enable are disabled (BHE, BLE HIGH),
or during an active write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “Truth Table” on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
www.DataSheet4PUO.cWoEmR DOWN
CIRCUIT
DATA IN DRIVERS
A10
A9
A8
A7
AA65 256K x 16
A4 RAM Array
A3
A2
A1
A0
COLUMN DECODER
CE
BHE
BLE
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05441 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 06, 2010
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CY62147EV18 MoBL®
Thermal Resistance
Parameter[10]
Description
JA Thermal resistance
(Junction to ambient)
JC Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
VFBGA
Package
75
10
Unit
C / W
C / W
Figure 2. AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
R2
VCC
10%
GND
Rise Time = 1 V/ns
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
R1
R2
RTH
VTH
1.80V
13500
10800
6000
0.80
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ[11] Max
VDR
ICCDR[12]
VCC for data retention
Data retention current
VCC = 1.0 V, CE > VCC – 0.2 V or
(BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V
or VIN < 0.2 V
1.0
–
–
0.5
–
5
tCDR[10]
tR[13]
Chip deselect to data retention time
Operation recovery time
0–
55 –
–
–
Unit
V
A
ns
ns
Figure 3. Data Retention Waveform[14]
VCC
CE or
www.DataSBhHeEe.tB4LUE.com
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.0 V
VCC(min)
tR
Notes
10. Tested initially and after any design or process changes that may affect these parameters
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s
14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 38-05441 Rev. *H
Page 5 of 16
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CY62147EV18 MoBL®
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
55 CY62147EV18LL-55BVXI
51-85150 48-ball VFBGA (Pb-free)
Contact your local Cypress sales representative for availability of other parts.
Ordering Code Definition
CY 621 4 7 E V18 LL 45/55 XXX X
Temperature grade:
I = Industrial
Package type:
BVX: VFBGA (Pb-free)
Speed grade
Low power
Voltage range = 3 V typical
E = Process Technology 90 nm
Bus width = x16
Density = 16 Mbit
621 = MoBL SRAM family
Company ID: CY = Cypress
Operating
Range
Industrial
www.DataSheet4U.com
Document #: 38-05441 Rev. *H
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