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PDF CY62126EV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62126EV30 | |
| Descripción | 1-Mbit (64K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62126EV30 MoBL®
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
■ High speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62126DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Offered in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
64K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05486 Rev. *N
BHE
WE
CE
OE
BLE
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 5, 2015
1 page  
CY62126EV30 MoBL®
Capacitance
Parameter [8]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [8]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
10 pF
10 pF
Test Conditions
Still Air, soldered on a 4.25 × 1.125 inch,
two-layer printed circuit board
48-ball VFBGA 44-pin TSOP II
Package
Package
Unit
58.85
28.2 °C/W
17.01
3.4 °C/W
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
VCC 10% 90%
90%
10%
R2 GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
2.2 V–2.7 V
16600
15400
8000
1.2
2.7 V–3.6 V
1103
1554
645
1.75
Unit
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05486 Rev. *N
Page 5 of 18
5 Page 
CY62126EV30 MoBL®
Truth Table
CE[29] WE
HX
LX
LH
LH
OE
X
X
L
L
LHL
L HH
L HH
L HH
LLX
LLX
LLX
BHE
X
H
L
H
L
L
H
L
L
H
L
BLE
Inputs/Outputs
X High Z
H High Z
L Data out (I/O0–I/O15)
L Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
L High Z
L High Z
H High Z
L Data in (I/O0–I/O15)
L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Mode
Deselect/power down
Output disabled
Read
Read
Read
Output disabled
Output disabled
Output disabled
Write
Write
Write
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
29. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05486 Rev. *N
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY62126EV30.PDF ] | |
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