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PDF CY2XF34 Data sheet ( Hoja de datos )
| Número de pieza | CY2XF34 | |
| Descripción | High Performance LVPECL Oscillator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2XF34
High Performance LVPECL Oscillator with
Frequency Margining – Pin Control
High Performance LVPECL Oscillator with Frequency Margining - Pin Control
Features
■ Low Jitter Crystal Oscillator (XO)
■ Less than 1 ps Typical RMS Phase Jitter
■ Differential LVPECL Output
■ Output Frequency from 50 MHz to 690 MHz
■ Two Frequency Margining Control Pins (FS0, FS1)
■ Factory Configured or Field Programmable
■ Integrated Phase-Locked Loop (PLL)
■ Supply Voltage: 3.3 V or 2.5 V
■ Pb-Free Package: 5.0 × 3.2 mm LCC
■ Commercial and Industrial Temperature Ranges
Functional Description
The CY2XF34 is a high performance and high frequency Crystal
Oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed through two select pins, allowing
easy frequency margin testing in applications.
The CY2XF34 is available as a factory configured device or as
a field programmable device.
Logic Block Diagram
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
OUTPUT
DIVIDER
4 CLK
5 CLK#
FS1 1
FS0 2
FREQUENCY
SELECT DECODE
Pinouts
Figure 1. Pin Diagram - 6-pin Ceramic LCC
FS1 1
FS0 2
VSS 3
6 VDD
5 CLK#
4 CLK
Pin Definitions
Pin
1, 2
4, 5
6
3
Name
FS1, FS0
CLK, CLK#
VDD
VSS
I/O Type
CMOS input
LVPECL output
Power
Power
Frequency select
Differential output clock
Supply voltage: 2.5 V or 3.3 V
Ground
Description
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-53149 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 13, 2011
1 page  
CY2XF34
DC Electrical Characteristics (continued)
Parameter
Description
CIN0[4]
CIN1[4]
Input Capacitance, FS0 pin
Input Capacitance, FS1 pin
Condition
Min Typ Max
– 15
–
–4
–
AC Electrical Characteristics
The AC Electrical Characteristics for part CY2XF34 are as follows [4]
Parameter
Description
FOUT
Output Frequency[5]
FSC
Frequency Stability, commercial
devices[6]
Condition
TA = 0 °C to 70 °C
Min Typ Max
50 – 690
– – ±35
FSI
Frequency Stability, industrial
devices[6]
TA = –40 °C to 85 °C
– – ±55
AG Aging, 10 years
– – ±15
TDC Output Duty Cycle
F 450 MHz, measured at zero
crossing
45 50 55
F > 450 MHz, measured at zero
crossing
40 50 60
TR, TF
TLOCK
TLFS
Output Rise and Fall Time
Startup Time
Re-lock Time
20% and 80% of full output swing
0.2 0.4 1.0
Time for CLK to reach valid frequency
–
–
10
measured from the time VDD = VDD(min)
Time for CLK to reach valid frequency
–
–
10
from FS0 or FS1 pin change
TJitter()
RMS Phase Jitter (Random)
fOUT = 106.25 MHz (12 kHz–20 MHz)
–
1
–
Typical Output Characteristics
Figure 2. 2.5V Supply and Termination to VDD–1.5 V, minimum VDD and maximum TA
0.9 1.40
Unit
pF
pF
Unit
MHz
ppm
ppm
ppm
%
%
ns
ms
ms
ps
0.8
1.35
0.7
1.30
0.6
1.25
0.5
0.4
0
100 200 300 400 500 600 700
Frequency (MHz)
1.20
0
100 200 300 400 500 600 700
Frequency (MHz)
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. This parameter is specified in CyberClocks Online software.
6. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
Document Number: 001-53149 Rev. *E
Page 5 of 12
5 Page 
CY2XF34
Document History Page
Document Title: CY2XF34 High Performance LVPECL Oscillator with Frequency Margining – Pin Control
Document Number: 001-53149
Revision
ECN
Orig. of Submission
Change
Date
Description of Change
** 2704379 KVM/PYRS 05/11/09 New datasheet
*A
2734005 WWZ
07/09/09 Post to external web
*B
2761926
KVM
09/10/09 Revised maximum output rise and fall times
Added Absolute Maximum Conditions table
*C
2898472
KVM 03/24/2010 Moved ‘xxx’ parts to Possible Configurations table.
Updated package diagram.
*D 3199911 BASH 03/18/2011 Changed status from Preliminary to Final.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
*E 3281222 BASH 06/13/2011 Swapped FS0 and FS1 in Logic Block Diagram, Pinouts and Pin Definition on
page 1.
Document Number: 001-53149 Rev. *E
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY2XF34.PDF ] | |
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