PDF CY2XP304 Data sheet ( Hoja de datos )

Número de pieza	CY2XP304
Descripción	High-Frequency Programmable PECL Clock Generation Module
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • Period jitter peak-peak 125MHz(max.) = 55 ps • Four low-skew LVPECL outputs • Phase-locked loop (PLL) multiplier select • Serially-configurable multiply ratios • Eight-bit feedback counter and six-bit reference counter for high accuracy • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • High-speed PLL bypass mode to 1.5 GHz • 36-VFBGA, 6 × 8 × 1 mm • 3.3V operation Block Diagram PLL_MULT XIN XOUT SER CLK SER DATA INA INAB CLK_SEL XTAL OSCILLATOR PLL xM 0 1 CLK0 CLK0B CLK1 CLK1B CLK2 CLK2B CLK3 CLK3B Pin Configuration C Y2X P 3 0 4 3 6 V F B G A P IN C O N F IG U R A T IO N T O P V IE W CLK 0 6 5 VDDA 4 GND Xo u t 3 2 Xin VDDB 1 A CLK 0B GND S E R_D A TA S E R_CL K GND VDDB B CLK 1 CLK 1B CLK 2 T O P V IE W GND GND GND C P LL_M UL T D CLK _S E L E CLK 2B GND GND IN A F CLK 3 GND V DDB VDDB GND IN A B G CLK 3B V DDA V DDA NC VDDA VDDA H Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 www.DDaotcauSmheeent4tU#.:n3e8t -07589 Rev. B Revised July 28, 2004 1 page Absolute Maximum Conditions Parameter VCC VCC VTT VIN VOUT LUI TS TA TJ ØJc ØJa ESDh MSL GATES Description Supply Voltage Operating Voltage Output Termination Voltage Input Voltage Output Voltage Latch Up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Crystal Requirements Condition Non-functional Functional Relative to VCC[1] Relative to VCC[1] Relative to VCC[1] Functional Non-functional Functional Non-functional Functional Functional Assembled die Requirements to use parallel mode fundamental xtal. External capacitors are required in the crystal oscillator circuit. Please refer to the application note entitled Crystal Oscillator Topics for details. Crystal Requirements Parameter XF Frequency Description DC Electrical Specifications Parameter VDD VIL VIH RPUP tPU Description Supply voltage Input signal low voltage at pin PLL_MULT Input signal high voltage at pin PLL_MULT Internal pull-up resistance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Operating Conditions Parameter TA Description Commercial Temperature Industrial Temperature Note: 1. Where VCC is 3.3V±5% CY2XP304 Min. Max. –0.3 4.6 3.135 3.465 –0.3 –0.3 VCC – 2 VCC + 0.3 VCC + 0.3 100 –65 +150 –40 +85 – 150 11.38 85.83 2000 3 50 Unit V V V V V mA °C °C °C °C/W °C/W V N.A. Ea. Min. 10 Min. 3.135 – 0.65 10 0.05 Max. 31.25 Max. 3.465 0.35 – 100 500 Unit MHz Unit V V V kΩ ms Min. 0 –40 Max. 70 85 Unit °C °C Document #: 38-07589 Rev. B Page 5 of 11 5 Page Document History Page Document Title: CY2XP304 High-Frequency Programmable PECL Clock Generation Module Document Number: 38-07589 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 129898 12/02/03 RGL New Data Sheet A 235868 See ECN RGL Updated Jitter spec based on the characterization report B 247601 See ECN RGL/GGK Changed VOH and VOL to match the Char Data CY2XP304 Document #: 38-07589 Rev. *B Page 11 of 11 11 Page

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Número de pieza	Descripción	Fabricantes
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