PDF CY2XP306 Data sheet ( Hoja de datos )

Número de pieza	CY2XP306
Descripción	High-frequency Programmable PECL Clock Generation Module
Fabricantes	Cypress Semiconductor
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No Preview Available ! PRELIMINARY CY2XP306 High-frequency Programmable PECL Clock Generation Module Features • 60 ps typical Cycle-to-Cycle Jitter • 30 ps typical Output-Output Skew • Phase-locked loop (PLL) multiplier select • LVTTL or XO Input; Six LVPECL Outputs • Selectable Output Divider (/2) Block Diagram FSELA PLL_MULT XIN/REF XOUT SER CLK SER DATA XTAL OSCILLATOR PLL xM MR FSELB Pin Configuration (Top View) C Y 2X P 306 36 V FB G A P IN C O N F IG U R A T IO N QA1 6 5 VDDA 4 GND XOUT 3 2 XIN VDDB 1 A QA1# GND SER_ DATA SER_ CLK GND VDDB B QA2 QB2 QB2# GND C QA2# PLL_ M ULT D • 1–133 MHz Input Frequency Range • 62.5–500 MHz Output Frequency Range • 36-pin VFBGA, 6 × 8 × 1 mm • 3.3V operation • Serially Configurable Multiply Ratios 0 1 /1 /2 0 1 QA1 QA1# QA2 QA2# QA3 QA3# QB1 QB1# QB2 QB2# QB3 QB3# T O P V IE W QA3 QA3# QB1 GND QB3 VDDB QB3# VDDB GND MR FSELA FSELB E FG QB1# VDDA VDDA NC VDDA VDDA H Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 www.DDaotcauShmeetn4tU#.:n3et8-07725 Rev. A Revised April 8, 2005 1 page PRELIMINARY CY2XP306 Absolute Maximum Conditions Parameter VDD VDD VTT VIN VOUT LUI TS TA TJ ØJc ØJa ESDh MSL Description Supply Voltage Operating Voltage Output Termination Voltage Input Voltage Output Voltage Latch Up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Condition Non-functional Functional Relative to VDD[1] Relative to VDD[1] Relative to VDD[1] Functional Non-functional Functional Non-functional Functional Functional Min. Max. –0.3 4.6 3.135 3.465 –0.3 –0.3 VDD – 2 VDD + 0.3 VDD + 0.3 100 –65 +150 –40 +85 – 150 11.48 85.8 2000 3 Unit V V V V V mA °C °C °C °C/W °C/W V N.A. Crystal Requirements Requirements to use parallel mode fundamental xtal. External capacitors are required in the crystal oscillator circuit. Please refer to the application note entitled Crystal Oscillator Topics for details. Crystal Requirements Parameter XF Frequency Description Min. 10 Max. 31.25 Unit MHz DC Specifications (VDD = 3.3 V ± 5%, Commercial and Industrial Temperature) Parameter Description Min. Max. VDD VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 RPUP tPU Supply voltage 3.135 3.465 Input signal low voltage at pin PLL_MULT – 0.35 Input signal high voltage at pin PLL_MULT 0.65 – Input signal low voltage at pins REF – 0.8 Input signal high voltage at pins REF 2.0 – LVPECL input signal low voltage at pins MR, FSELA, FSELB VDD – 1.945 VDD – 1.625[3] LVPECL input signal high voltage at pins MR, FSELA, FSELB VDD – 1.165[3] VDD – 0.88 Internal pull-up resistance 10 100 Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 IEE Maximum Quiescent Supply Current without Output Termi- – 150 nation Current VOL LVPECL Output Low Voltage VDD = 3.3V ± 5% VOH LVPECL Output High Voltage IOL = –5 mA[2] VDD – 1.995 IOH = –30 mA[2] VDD – 1.25 VDD – 1.5 VDD – 0.7 Note: 1. Where VDD is 3.3V±5% 2. Equivalent to a termination of 50Ω to VTT. 3. VIL3 will operate down to GND; VIH3 will operate up to VDD. Unit V VDD VDD V V V V kΩ ms mA V V Document #: 38-07725 Rev. A Page 5 of 9 5 Page

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Número de pieza	Descripción	Fabricantes
CY2XP304	High-Frequency Programmable PECL Clock Generation Module	Cypress Semiconductor
CY2XP306	High-frequency Programmable PECL Clock Generation Module	Cypress Semiconductor

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