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PDF SI7232DN Data sheet ( Hoja de datos )
| Número de pieza | SI7232DN | |
| Descripción | Dual N-Channel 20-V (D-S) MOSFET | |
| Fabricantes | Vishay Siliconix | |
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Si7232DN
Vishay Siliconix
Dual N-Channel 20-V (D-S) MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
0.0164 at VGS = 4.5 V
20 0.020 at VGS = 2.5 V
0.024 at VGS = 1.8 V
ID (A)
25f
25f
24.6
Qg (Typ.)
12 nC
PowerPAK® 1212-8
3.30 mm
S1
1
G1
2
3.30 mm
S2
3 G2
4
D1
8
D1
7
D2
6 D2
5
Bottom View
Ordering Information: Si7232DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• DC/DC
• Notebook System Power
• POL
D1
D2
G1 G2
S1
N-Channel MOSFET
S2
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Pulsed Drain Current
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Continuous Source-Drain Diode Current
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
TC = 25 °C
TA = 25 °C
L = 0.1 mH
TC = 25 °C
Maximum Power Dissipation
TC = 70 °C
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)c, d
VDS
VGS
ID
IDM
IS
IAS
EAS
PD
TJ, Tstg
Limit
20
±8
25f
23.8
10a, b
8a, b
40
19
2.2a, b
15
11
23
14.8
2.6a, b
1.7a, b
- 55 to 150
260
Unit
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambienta, e
Maximum Junction-to-Case (Drain)
t ≤ 10 s
Steady State
RthJA
RthJC
38
4.3
48 °C/W
5.4
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Maximum under steady state conditions is 94 °C/W.
f. Package Limited.
Document Number: 68986
S09-1499-Rev. B, 10-Aug-09
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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40 25
Si7232DN
Vishay Siliconix
32 20
24 Package Limited
16
15
10
85
0
0 25 50 75 100 125 150
TC - Case Temperature (°C)
Current Derating*
0
25 50 75 100 125 150
TC - Case Temperature (°C)
Power Derating
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 68986
S09-1499-Rev. B, 10-Aug-09
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AN822
Vishay Siliconix
105
Spreading Copper (sq. in.)
95
85
75
65
55
0%
45
100 %
50 %
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
130
120 Spreading Copper (sq. in.)
110
100
90
80
50 %
100 %
70
60 0 %
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor-
mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attrac-
tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com
4
Document Number 71681
03-Mar-06
Datasheet pdf - http://www.DataSheet4U.net/
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