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PDF ADP2442 Data sheet ( Hoja de datos )
| Número de pieza | ADP2442 | |
| Descripción | DC-to-DC Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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36 V,1 A, Synchronous, Step-Down, DC-to-DC
Regulator with External Clock Synchronization
Data Sheet
ADP2442
FEATURES
Wide input voltage range from 4.5 V to 36 V
Low minimum on time of 50 ns typical
Maximum load current of 1 A
High efficiency of up to 94%
Adjustable output down to 0.6 V
±1% output voltage accuracy
Adjustable switching frequency from 300 kHz to 1 MHz
External synchronization from 300 kHz to 1 MHz
Pulse skip mode or forced fixed frequency mode
Precision enable input pin (EN)
Open-drain power good
Internal soft start
Overcurrent-limit protection
Shutdown current of less than 15 µA
UVLO and thermal shutdown
12-lead, 3 mm × 3 mm LFCSP package
Supported by the ADIsimPower™ tool set
APPLICATIONS
Point of load applications
Distributed power systems
Industrial control supplies
Standard rail conversion to 24 V/12 V/5 V/3.3 V
GENERAL DESCRIPTION
The ADP2442 is a constant frequency, current mode control,
synchronous, step-down, dc-to-dc regulator that is capable of
driving loads of up to 1 A with excellent line and load regulation
characteristics. The ADP2442 operates with a wide input voltage
range from 4.5 V to 36 V, which makes it ideal for regulating power
from a wide variety of sources. In addition, the ADP2442 has
very low minimum on time (50 ns) and is, therefore, suitable for
applications requiring a very high step-down ratio.
The output voltage can be adjusted from 0.6 V to 0.9 × VIN.
High efficiency is obtained with integrated low resistance
N-channel MOSFETs for both high-side and low-side devices.
The switching frequency is adjustable from 300 kHz to 1 MHz with
an external resistor. The ADP2442 also has an accurate power-good
(PGOOD) open-drain output signal.
The ADP2442 offers the flexibility of external clock synchroni-
zation. The switching frequency can be synchronized to an external
clock, applied to the SYNC/MODE pin. The ADP2442 can also
be configured to operate in the forced fixed frequency mode for
low EMI or power saving mode to reduce the switching losses at
light load.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
TYPICAL CIRCUIT CONFIGURATION
C2
VOUT
RTOP
RBOTTOM
RCOMP
CCOMP
C1
CBOOST
FB VIN
ADP2442
COMP
SW
PGND
EN
VIN
CIN
VOUT
COUT
RFREQ
Figure 1.
The ADP2442 uses hiccup mode to protect the IC from short
www.DataSheet.net/ circuits or from overcurrent conditions on the output. The internal
soft start limits inrush current during startup for a wide variety of
load capacitances. Other key features include input undervoltage
lockout (UVLO), thermal shutdown (TSD), and precision enable
(EN), which can also be used as a logic level shutdown input.
The ADP2442 is available in a 3 mm × 3 mm, 12-lead LFCSP
package and is rated for a junction temperature range from
−40°C to +125°C.
100
90 VOUT = 12V
80
70
VOUT = 5V
60
50
VOUT = 3.3V
40
30
20
10
VIN = 24V
PWM = 300kHz
0
0.01
0.1
LOAD (A)
1
Figure 2. Efficiency vs. Load Current, VIN = 24 V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN to PGND
EN to AGND
SW to PGND
BST to PGND
VCC to AGND
BST to SW
FREQ, PGOOD, SYNC/MODE, COMP,
FB to AGND
PGND to AGND
Operating Junction Temperature
Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +40 V
−0.3 V to +40 V
−0.3 V to +40 V
−0.3 V to +45 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
±0.3 V
−40°C to +125°C
−65°C to +150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADP2442
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages based on
a 4-layer standard JEDEC board.
Table 3. Thermal Resistance
Package Type
12-Lead LFCSP
θJA θJC Unit
40 2.4 °C/W
ESD CAUTION
www.DataSheet.net/
Rev. 0 | Page 5 of 36
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
Data Sheet
200
175 MINIMUM OFF
150
125
100
75
50 MINIMUM ON
25
0
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 28. Minimum On Time and Minimum Off Time vs. Temperature
260
240
220
200
180
160
140
120
100
–50
–25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 29. High-Side RDS(ON) vs. Temperature
150
1200
1100
1000
fSW = 1MHz
900
800
fSW = 700kHz
700
600
500
400
fSW = 300kHz
300
200
–50 –30 –10
10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 30. Switching Frequency vs. Temperature
ADP2442
1.80
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
1.58
1.56
1.54
1.52
1.50
–50
VIN = 36V
VIN = 4.5V
0 50 100
TEMPERATURE (°C)
Figure 31. Current Limit vs. Temperature
150
180
160
140
120
100
80
60
40
www.DataSheet.net/
20
0
–50 –30 –10
10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 32. Low-Side RDS(ON) vs. Temperature
VOUT
1
INDUCTOR CURRENT
4
SW
2
VIN = 24V
VOUT = 5V
fSW = 700kHz
NO LOAD
SYNC/MODE = AGND
CH1 20.0mV BW CH2 10.0V
M4.00µs A CH4 116mA
CH4 200mA Ω T 50.40%
Figure 33. Pulse Skip Mode, VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, No Load,
SYNC/MODE = AGND
Rev. 0 | Page 11 of 36
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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| PDF Descargar | [ Datasheet ADP2442.PDF ] | |
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