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PDF HY27UG088GDB Data sheet ( Hoja de datos )
| Número de pieza | HY27UG088GDB | |
| Descripción | 8Gb NAND FLASH | |
| Fabricantes | Hynix | |
| Logotipo |  |
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1
HY27UG088G(5/D)B Series
8Gbit (1Gx8bit) NAND Flash
8Gb NAND FLASH
HY27UG088G(5/D)B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.2 / Jan. 2008
1
Free Datasheet http://www.datasheet4u.com/
1 page  
1
HY27UG088G(5/D)B Series
8Gbit (1Gx8bit) NAND Flash
9&&
&( ,2a,2
&(
:( 5%
5( 5%
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:3
966
Figure1: Logic Diagram
IO7 - IO0
CLE
ALE
CE1, CE2
RE
WE
WP
R/B1, R/B2
Vcc
Vss
NC
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.2 / Jan. 2008
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
1
HY27UG088G(5/D)B Series
8Gbit (1Gx8bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be
high. See Figure 5 and Table 12 for details of the timings requirements. Command codes are always applied on IO7:0
regardless of the bus configuration. (x8)
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses
for the 8Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable
low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify-
ing operation (write/erase) the Write Protect pin must be high. See Figure 6 and Table 12 for details of the timings
requirements. Addresses are always applied on IO7:0 regardless of the bus configuration (x8).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serial and timed
by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch
Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 7 and
Table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the EDC
register content and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low,
Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 8,9,11,12,13 and Table 12
for details of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modifying operation does not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protec-
tion even during the power up.
2.6 Standby
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.2 / Jan. 2008
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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