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PDF APL3513 Data sheet ( Hoja de datos )

Número de pieza APL3513
Descripción 2A High Side Load Switches
Fabricantes ANPEC 
Logotipo ANPEC Logotipo



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APL3513
2A High Side Load Switches
Features
70mHigh Side MOSFET
Wide Supply Voltage Range: 2.7V to 5.5V
Current-Limit and Short-Circuit Protections
Over-Temperature Protection
Fault Indication Output
Logic Level Enable Pin
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
Cellular Telephones
Digital Still Cameras
Hot Swap Supplies
Notebook Computers
Personal Communication Devices
Personal Digital Assistants (PDAs)
General Description
The APL3513 is a power-distribution switch with some
protection that can deliver current up to 2A. The device
incorporates a 70mN-channel MOSFET power switch
that is controlled by an enable logic pin.
The protection features include current-limit protection,
short-circuit protection, and over-temperature protection.
The device limits the output current at current limit thresh-
old level. When V drops below V -1V, the devices limit
OUT
IN
the current to a lower and safer level. The over-tempera-
ture protection limits the junction temperature below
140oC in case of short circuit or over load conditions.
Simplified Application Circuit
5V VOUT
VIN VOUT
APL3513
EN EN
GND
Pin Configuration
VIN 1
VOUT 2
EN 3
GND 4
8 VIN
7 VIN
6 VIN
5 VIN
APL3513
TDFN2x2-8(Top View)
= Exposed Pad
(connected to ground plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - May., 2010
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/

1 page




APL3513 pdf
APL3513
Typical Operating Characteristics (Cont.)
Current-Limit Response vs. Output
Peak Current
300
VIN = 5V, TA=25oC
250
200
150
100
50
0
0 2 4 6 8 10 12
Output Peak Current (A)
EN Pin Threshold Voltage vs.
Junction Temperature
3.0
2.5
2.0 EN Rising
1.5 EN Falling
1.0
RLOAD =50,
CIN = COUT =33µF/Elctrolytic
0.5
-50 0
50 100
Junction Temperature (oC)
150
Turn-Off Leakage Current vs.
Junction Temperature
4.0
VIN =5V, RLOAD =0,
3.5 CIN = COUT =33µF/Elctrolytic
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50
0 50 100
Junction Temperature (oC)
150
Copyright © ANPEC Electronics Corp.
Rev. A.2 - May., 2010
5
Short-Circuit Output Current vs.
Input Voltage
1.4
TA=25oC
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.5
EN Pin Threshold Voltage vs.
Input Voltage
EN Rising
EN Falling
VIN =5V, RLOAD =50,
CIN = COUT =33µF/Elctrolytic, TA=25oC
3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
UVLO Threshold Voltage vs.
Junction Temperature
3.2
2.8
UVLO Rising
2.4
2.0 UVLO Falling
1.6
1.2 VIN Increasing, IOUT =15mA,
CIN = COUT =33µF/Elctrolytic
0.8
-50 0
50 100
Junction Temperature (oC)
150
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/

5 Page





APL3513 arduino
APL3513
Application Information
Input Capacitor
A 1µF ceramic bypass capacitor from VIN to GND, located
near the APL3513, is strongly recommended to suppress
the ringing during short circuit fault event. Without the
bypass capacitor, the output short may cause sufficient
ringing on the input (from supply lead inductance) to dam-
age internal control circuitry.
Output Capacitor
A bypassing 0.1µF ceramic capacitor improves the immu-
nity of the device to short-circuit transients. A low-ESR
high capacitance between VOUT and GND is suggested to
reduce the voltage droop during load transient.
Layout Consideration
The PCB layout should be carefully performed to maxi-
mize thermal dissipation and to minimize voltage drop,
droop and EMI. The following guidelines must be
considered:
1. Please place the input capacitors near the VIN pin as
close as possible.
2. Output decoupling capacitors for load must be placed
near the load as close as possible for decoupling high-
frequency ripples.
3. Locate APL3513 and output capacitors near the load to
reduce parasitic resistance and inductance for excel-
lent load transient performance.
4. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground plane
of the load.
5. Keep VIN and VOUT traces as wide and short as possible.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - May., 2010
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/

11 Page







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