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PDF SPMC02A Data sheet ( Hoja de datos )
| Número de pieza | SPMC02A | |
| Descripción | MICROCONTROLLER | |
| Fabricantes | Sunplus | |
| Logotipo |  |
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SPMC02A
MICROCONTROLLER
GENERAL DESCRIPTION
SUNPLUS SPMC02A contains a SUNPLUS 8 bit Micro-Controller
Units (MCU), 4.5K bytes ROM, 128 bytes SRAM and 2 8-bit
Timers. The advanced sub-micron CMOS process technology
ensures SPMC02A‘s high performance, high reliability and
advanced functions. In addition, SPMC02A also provides high
sink current with slow output transition port pins, multi external
interrupt pins, Low Voltage Reset (LVR) function, and multi
oscillator options. SPMC02A offers one of the best
cost/performance ratios in the industry.
BLOCK DIAGRAM
XO/R
XI
VDD
VSS
OSC.
CKT
4.5K bytes ROM
$600~$FFF &
$1800~$1FFF
128 bytes RAM
$80 ~ $FF
8 - bit CPU
PA3-0
PA7
PC7-0
RESET(PB4)
IRQ(PB5)
PA6
PB3-1
PD3-0
TIMER 1
& RTI
& Watch_Dog timer
I/O PORT
&
External Interrupt
/13
I/O PORT
&
External RESET Pin
/1
I/O PORT
&
External IRQ Pin
/1
I/O PORT
/8
Interrupt Generator
&
RESET generator
TIMER 2 &
6 bits PWM
waveform generator
I/O PORT
&
/1 External CLOCK Pin
I/O PORT &
PWM waveform
output
/1
I/O PORT &
2 set Comparator
/3 circuit
PB6
PB7
PA4,PA5
PB0
FEATURES
Built-in 8-bit Sunplus CPU core and up to 6.0MHz clock
operation
128 bytes SRAM
4.5K bytes ROM for users' program
On-chip RC oscillator (only one external resistor needed) or
crystal input or external clock input
Up to 14 external interrupt pins.
1 I/O can be with RESET input selected by mask option.
4 I/Os with Slow output transition Function
1 8-bits read-only timer with Real Time Interrupt
1 8-bits re-loadable Timer with programmable 8 stage
pre-scalar.
1 external clock input pin for Timer 2
1 6-bit PWM waveform generator
1 Watchdog timer
Built-in two Comparators
Power-saving STOP & WAIT modes
Illegal address reset
Low voltage reset circuit
Operation Voltage Range: 2.4V - 5.5V
Provides Chip Form, Package in PDIP or SOIC.
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY
CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this
document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is
assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition,
SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or
failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
PAGE 1
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1 page  
SPMC02A
I/O AND CONTROL REGISTER
- see Appendix A, ~ G (I/O Diagram)
Total of 28 I/Os (grouped into four ports PA, PB, PC, and PD) are
provided. The descriptions are as follows:
1). The 8 I/Os are normal I/O ports: PA6, Port B (PB3 - 0) and
Port D (PD3 - 0).
2). There are 13 I/Os used for I/O or I/O with external interrupt.
The PA3 - 0 can be mask-option for I/O or I/O with
external interrupt.
The PA7 & PC7 - 0 can be programmed as I/O or I/O with
external interrupt.
3). There are 3 I/Os used to comparator function.
The PA4 and PA5 are comparator input pins.
The PB0 is reference voltage input pin for comparator.
4). The PB4 can be mask option to I/O or I/O with RESET pin.
5). The PB5 can be programmed as I/O or I/O with IRQ pin.
6). The PB6 can be programmed as I/O or I/O with external clock
input pin.
7). The PB7 can be programmed as I/O or I/O with PWM
waveform output pin.
1. PORT A (PA7 - 0): (see Appendix A, B, C)
ADDR
REGISTER
7
6
5
4
3
$0000 PORT A DATA
DATA
DATA
DATA
DATA
DATA
$0002 DIRECTION 0
In
In
In
In
In
1 Out Out Out Out Out
$0009 Pull-Up/Down
0
1
Always*
Pull-Up
Always
Pull-Up
Enable
Disable
Enable
Disable
Enable
Disable
Up/Down resistor
5KΩ
5KΩ
100KΩ
100KΩ
100KΩ
Source/sink current
-/8mA
-/8mA
-8/8mA
-8/8mA
-8/8mA
Special Function
Ext. INT
- Comparator Comparator Ext. INT
Note: This bit is defined as SLE bit. Please refer to SLOW TRANSITION ENABLE for more detail.
2
DATA
In
Out
Enable
Disable
100KΩ
-8/8mA
Ext. INT
1
DATA
In
Out
Enable
Disable
100KΩ
-8/8mA
Ext. INT
0
DATA
In
Out
Enable
Disable
100KΩ
-8/8mA
Ext. INT
2. PORT A DATA REGISTER ($0000 PA)
PortA’s output data will be determined by $0000 PA Data Register
when PortA is programmed as output. Any read of PortA Data
Register will return the logical state of the I/O pin when PortA is
programmed as input. The PA Data Register is set to ‘0’ when a
RESET is occurred.
3. PORT A DATA DIRECTION REGISTER ($0002 DPA)
The PortA can be programmed as input or output by $0002 DPA
Register. When DPA = ’1’, the corresponding pin(s) is (are)
programmed as output. When DPA = ’0’, the corresponding pin(s)
is (are) programmed as input. The DPA is set to ‘0’ (input) when a
RESET is occurred.
4. PORT A PULL-UP/DOWN CONTROL REGISTER
($0009 RPA)
PA5 - 0 pull-up/down resistors can be mask option to pull-up or
pull-down, but PA6, PA7 are always pull-up. The register, RPA, is
used to enable or disable the pull-up/down resistors on PA5 - 0.
When RPA = ’0’, it will enable pull-up/down resistor of
corresponding pins (PA5 - 0) at Input mode. When RPA = ’1’, it
will disable the corresponding pull-up/down resistors at input
mode only. No pull-up/down resistor is available at output mode.
The RPA will be set to ‘0’ (enabling mode) by RESET.
© Sunplus Technology Co., Ltd.
PAGE 5
NOV. 07, 2000
Version: 1.5
Free Datasheet http://www.0PDF.com
5 Page 
SPMC02A
5. PC7 - 0 INTERRUPT (see Appendix A, I)
The PC7 - 0 interrupt inputs are rising edge trigger. It is controlled
by IRQE2 ($0006 bit4). When PC7 - 0 interrupt occurred, the
IRQF2 ($0006 bit5) will be set. To clear IRQF2, disable IRQE2
first and then set IRQE2 again. As stated above, IRQF2 will be
cleared to ‘0’.
Example: use IRQ pin, PA3 - 0, PA7 and PC7 - 0 as interrupt.
LDA #00
STA DPA
;set PA, PC port to
;input
STA DPC
LDA #%11010011 ;enable IRQ, PA3 - 0,
;PA7, PC7 - 0 IRQ and
;clear INT Flag
STA IRQS
;IRQS = $0006
....
;other working
IRQVacter: LDA IRQS
;Interrupt
;subroutine
STA IRQS_STU
;IRQ status register
AND #%00000100 ;check interrupt of
;PA7
BNE PA7_IRQ
LDA IRQS_STU
AND #%00100000 ;check interrupt
PC7 - 0
BNE PC_IRQ
PA03_IRQ: LDA IRQS_STU
AND #%00001000 ;check interrupt of
;PA3 - 0
BEQ IRQ_END
;no PA3 - 0, PA7,
;PC7 - 0 & external IRQ
;pin
LDA PA
AND #%00001111 ;check PA3 - 0 create
;IRQ
BNE PA03_In
IRQP_In: ....
;IRQ pin interrupt
;works something.
JMP PA03_END
PA03_In: ....
;PA3 - 0 interrupt
;work something.
PA03_END: LDA #%01010011
JMP IRQ_END
PA7_IRQ: ....
LDA #%10010011
JMP IRQ_END
PC_IRQ:
....
LDA IRQS_STU
AND #%11001111
STA IRQS
ORA #%00010011
IRQ_END:
STA IRQS
RTI
;set PA3 - 0, PA7,
;PC7 - 0 clear
;PA3 - 0 Flag. Don‘t
;clear PA7, PC7 - 0
;Flag for next IRQ of
;PA7, PC7 - 0.
;PA7 interrupt works
;something.
;set PA3 - 0, PA7,
;PC7 - 0 & clear PA7
;Flag, Don‘t
;clear PA3 - 0,PC Flag
;for next IRQ of
;PA3 - 0,PC
;PC7 - 0 interrupt
;work something.
;clear PC7 - 0 IRQ Flag
;set PA3 - 0, PA7,
;PC7 - 0 & clear PC
;Flag, Don‘t clear
;PA3 - 0, PA7 Flag for
;next IRQ
6. TIMER INTERRUPT (TIMER) (see Appendix J, K)
The TIMER INTERRUPT is generated when Timer1 or Timer2
overflows or a real time interrupt has occurred. The timer
interrupt flags (TOF1, TOF2, RTIF), enable bits (TOFE1, TOFE2,
RTIE) and timer interrupt acknowledge bits (TOFR1, TOFR2, and
RTIFR) are designed for the timer interrupt. There are located in
the Timer Control & Status Register 1 (TCS1) (address at $0004)
and Timer Control & Status Register 2 (TCS2) (address at $000E).
The I-bit in the Processor Status Flag (inside CPU) must be
cleared to ‘0’ for enabling interrupt (use CLI instruction). For
more details on settings of the Timer Control & Status Register
(TCS), please see the MULTI-FUNCTION TIMER section.
© Sunplus Technology Co., Ltd.
PAGE 11
NOV. 07, 2000
Version: 1.5
Free Datasheet http://www.0PDF.com
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