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PDF AK4679 Data sheet ( Hoja de datos )
| Número de pieza | AK4679 | |
| Descripción | 24bit Stereo CODEC | |
| Fabricantes | AKM | |
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[AK4679]
AK4679
24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP
GENERAL DESCRIPTION
The AK4679 is a 24bit stereo CODEC and a built-in Microphone-Amplifier, Receiver-Amplifier, Mono
Class-D Speaker-Amplifier, Cap-less Class-G Headphone-Amplifier and Line-Amplifier as well as
HF/Audio DSP. The AK4679 features AKM DSP core to deal with hands free function for wide band and
dual PCM I/F in addition to audio I/F that allows eas y interfacing in mobile phone designs with Bluetooth
I/F. The playback features also include 5-band Parametric EQ and Dynamic Range Control; therefore the
AK4679 can automatically adjus t the volume to a comfortable leve l that has no dist ortion and provides
great flexibility. The AK4679 is available in a 78pin BGA, utilizing less board space than competitive
offerings.
FEATURES
CODEC&Amp block
1. Recording Function (Stereo CODEC)
• 4 Stereo Input Selectors
• 4 Stereo Inputs (Single-ended) or 3 Mono Input (Full-differential)
• MIC Amplifier: +24dB ~ −6dB, 3dB step
• 2 Output MIC Power Supplies
• Digital ALC (Automatic Level Control): +36dB ~ −54dB, 0.375dB Step, Mute
• ADC CHARACTERISTICS: S/(N+D): 80dB, DR, S/N: 87dB (MIC-Amp=+18dB)
S/(N+D): 80dB, DR, S/N: 92dB (MIC-Amp=0dB)
• Stereo Digital MIC Interface
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• 3-band Programmable Notch Filter
• Audio Interface Format: 24/16bit MSB justified, 24/16bit I2S, 16bit DSP Mode
2. Playback Function (Stereo CODEC)
• Digital Volume (+6dB ~ −57.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ~ −54dB, 0.375dB Step, Mute
• Stereo Separation Emphasis
• Dynamic Range Control
• 5-band Parametric Equalizer
• Stereo Line Output (Selectable Full-differential / Single-ended)
• Mono Receiver-Amp
- BTL Output
- Output Power: 60mW @ 32Ω
- Analog Volume: +12 ~ −30dB & Mute, 3dB Step
• Cap-less Stereo Class-G Headphone-Amp
- Output Power: 25mW @ 32Ω, 45mW @ 16Ω
- Analog Volume: +6 ~ −62dB & Mute, 2dB Step
- Zero crossing Detection
- Pop Noise Free at Power-ON/OFF
• Mono Class-D Speaker-Amp
- BTL Output
- Short Protection Circuit
- Output Power: 1.1W @ 8Ω, SVDD=4.2V, THD+N = 10%
0.89W @ 8Ω, SVDD=4.2V, THD+N = 1%
- Analog Volume: +12 ~ −30dB & Mute, 3dB Step
- Pop Noise Free at Power-ON/OFF
• Audio Interface Format:
- 24/16bit MSB justified, 16bit LSB justified, 16/24bit I2S, 16bit DSP Mode
MS1402-E-06
-1-
2013/02
http://www.Datasheet4U.com
1 page  
[AK4679]
From L ch MIC-Amp
From Rc h MIC-Amp
PMADL or PMADR
ADC HPF1
DVDD
VSS2 VSS5
To Lch Output
To Rch Output
PMDAL or PMDAR
DAC
S
E
L
PMDRC
DRC
DASEL1-0
PMMIX
MIX1L MIX1R
PMPFIL
bit
HPF2
LPF
Stereo
Separation
3-band
Notch
ALC
MIX
Control
Register
Audio
I/F
PMEQ
DATT-A 5-band
SMUTE EQ
SVOLA
S
E
L
MIX2A
PMSRAO
MoMnoIX2C
MIX2B
SVB2-0 SVOLB
DATT-B
BVL6-0
CVL6-0 DATT-C
MIX3
PMSRBO
BIVOL
BIV2-0
PLL
PMOSC
PMPLL
OSC
SRCAO
SDOAD
SRCAI
PMPCMA
PCM I/F
(PORTA)
PMSRAI
PMPCMB
SRCBO
SDOBD
PCM I/F
(PORTB)
SRCBI
PMSRBI
TVDDA
SCLA
SDAA
PDNA
BICK
LRCK
SDTO
SDTI
MCKI
BICKA
SYNCA
SDTOA
SDTIA
BICKB
SYNCB
SDTOB
SDTIB
Figure 2. Digital Block Diagram
MS1402-E-06
-5-
2013/02
5 Page 
[AK4679]
D2
SDOUT4
GP1
O
Serial Data Output 4 Pin
DSP Programmable output 1 Pin
(SELDO4 bit = “0”)
(SELDO4 bit = “1”)
C2 I2CE
I Control Interface Mode Select Pin for DSP Block “H”: I2CE, “L”: SPI
C7
SCLK
CAD0
I
Serial Clock Input pin
Slave Address 0 Input pin
SPI (I2CE pin = “L”)
I2C (I2CE pin = “H”)
B8
CSN
SCLE
I
Chip select pin
Control Interface clock input pin
SPI (I2CE pin = “L”)
I2C (I2CE pin = “H”)
C5
SO O
SDAE I/O
Serial data output pin
Control Interface input/output acknowledge pin
SPI (I2CE pin = “L”)
I2C (I2CE pin = “H”)
C6
SI
CAD1
I
Serial data input pin
Slave Address 1 Input pin
SPI (I2CE pin = “L”)
I2C(I2CE pin = “H”)
E4 TEST
I Test pin (pull-down resistor) must be connected to VSS4.
Note 2. All input pins must not be allowed to float.
Note 3. I2CE and CAD0/1 pins must be fixed to “L” (VSS4) or “H” (TVDDE).
■ Handling of Unused Pin on the System
The unused input and output pins on the system should be processed appropriately as below.
Classification Pi n Name
MPWR1, MPWR2, SPP, SPN, RCP, RCN, HPL,
HPR, ROUT/LON, LOUT/LOP, RIN4, LIN4,
Analog
RIN3/IN3−, LIN3/IN3+, RIN2/IN2+, LIN2/IN2-,
RIN1/IN1−, LIN1/IN1+, CPA, CNA, CPB, CNB,
VEE, SPFIL
SDTO, SDTOA, SDTOB
STO/RDY, SDOUT3/GPO, SDOUT4/GP1
MCKI, SDTI, SDTIA, SDTIB, BICKA, SYNCA,
Digital
BICKB, SYNCB
LRCK, BICK
SYNC1, BCLK1, SDIN3, SDIN4, SYNC3/JX1,
BCLK3/JX0, TEST
Setting
These pins should be open.
These pins should be open.
These pins should be connected to VSS2.
These pi ns shoul d be connect ed t o VSS2
and M/S bit should be set to “0”.
These pins should be connected to VSS4
■ Pin States in DSP Power-down Mode
The table below shows pin states when the PDNE pin= “L”.
NO Pin Name I/O
Pin state
G3 STO
RDY
O Low
H1 SDOUT1
O SDIN2 data output
D6 SYNC2
O SYNC1 data output
F2 BCLK2 O
BCLK1 data output
C4 SDOUT2
O SDIN1 data output
F4
SDOUT3
GP0
O SDIN4 data output
D2
SDOUT4
GP1
O SDIN3 data output
C5
SO O
SDAE
Low level (I2CE pin = “L”: SPI)
I/O Hi-z
(I2CE pin = “H” :I2C)
MS1402-E-06
- 11 -
2013/02
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AK4679.PDF ] | |
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