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PDF MC74HC251A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC251A | |
| Descripción | High Performance Silicon Gate CMOS | |
| Fabricantes | ON Semiconductor | |
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MC74HC251A
8-Input Data Selector/
Multiplexer with
3-State Outputs
High−Performance Silicon−Gate CMOS
The MC54/74HC251 is identical in pinout to the LS251. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as
determined by the Address Inputs. The Output Enable pin must be a
low level for the selected data to appear at the outputs. If Output
Enable is high, both the Y and the Y outputs are in the
high−impedance state. This 3 −state feature allows the HC251 to be
used in bus−oriented systems.
The HC251 is similar in function to the HC251 which does not have
3−state outputs.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• These are Pb−Free Devices
http://onsemi.com
16
1
MARKING
16 DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
HC251AG
AWLYWW
1
16
TSSOP−16
HC
16
1
DT SUFFIX
CASE 948F
251A
ALYWG
G
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
D3
D2
D1
D0
Y
Y
OUTPUT
ENABLE
GND
1
2
3
4
5
6
7
8
16 VCC
15 D4
14 D5
13 D6
12 D7
11 A0
10 A1
9 A2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 0
1
Publication Order Number:
MC74HC251A/D
http://www.Datasheet4U.com
1 page  
MC74HC251A
SWITCHING WAVEFORMS
tr
INPUT D
tPLH
OUTPUT Y
90%
50%
10%
90%
50%
10%
tTLH
Figure 2.
tf
VCC
GND
tPHL
tTHL
INPUT A
tPLH
OUTPUT
Y OR Y
VALID
50%
50%
VALID
tPHL
Figure 4.
VCC
GND
tr
INPUT D
tPHL
OUTPUT Y
90%
50%
10%
90%
50%
10%
tTLH
tf
VCC
GND
tPLH
tTHL
Figure 3.
OUTPUT
ENABLE
Y OR Y
Y OR Y
50%
tPZL
50%
tPZH
50%
tPLZ
tPHZ
Figure 5.
VCC
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6.
*Includes all probe and jig capacitance
Figure 7.
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| Páginas | Total 9 Páginas | |
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