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Número de pieza | HD74HC107 | |
Descripción | Dual J-K Flip-Flops (with Clear) | |
Fabricantes | Hitachi Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de HD74HC107 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
No Preview Available ! HD74HC107
Dual J-K Flip-Flops (with Clear)
Description
This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the
clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is
independent of the clock and accomplished by a low level on the input.
Features
• High Speed Operation: tpd (Clock to Q) = 19 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Function Table
Inputs
Output
Clear
Clock
J
K
Q
Q
LX X X L H
H L L No change
H LHL H
H HL H L
H H H Toggle
HL
XX
No change
H H X X No change
H X X No change
1 page 19.20
20.32 Max
14
8
1 1.30 7
2.39 Max
Unit: mm
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25
+
–
0.10
0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-14
Conforms
Conforms
0.97 g
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet HD74HC107.PDF ] |
Número de pieza | Descripción | Fabricantes |
HD74HC10 | Triple 3-input NAND Gates | Hitachi Semiconductor |
HD74HC107 | Dual J-K Flip-Flops (with Clear) | Hitachi Semiconductor |
HD74HC107 | Dual J-K Flip-Flops | Renesas |
HD74HC108 | Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock) | Hitachi Semiconductor |
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