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Número de pieza | PLL52C63-01 | |
Descripción | Pentium/SDRAM Clock Generator | |
Fabricantes | PhaseLink | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PLL52C63-01 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! PLL52C63-01
Pentium/SDRAM Clock Generator with Integrated Buffers
FEATURES
n Generates all clock frequencies for Pentium (II), AMD
and Cyrix system requiring multiple CPU clocks.
n Supports up to16 Synchronous CPU clocks (4 CPU and
12 SDRAM) and 7 Synchronous PCI BUS clocks.
n Two 14.318Mhz reference clocks and one 2.5V IOAPIC
n One 24Mhz floppy clock and one 48Mhz USB clock.
n Power management control pins to stop CPU, SDRAM
or PCI BUS clocks.
n Supports 2-wire I2C serial bus interface.
n 50% duty cycle with low jitter
n Mixed voltage support from 3.0 to 5V or (VDDq2=2.5V)
n Available in 300mil 48 pin SSOP.
PIN INFORMATION
FREQUENCY SELECTION (MHz)
F2 F1 F0 PCLK/SDRAM
000
50
001
100
010
83.3
011
68.5
100
55
101
75
110
60
111
66.6
BCLK
25
50
41.6
34.2
27.5
37.5
30
33.3
BLOCK DIAGRAM
Note: F2,F1,F0 and MODE are selectable only during power-on. They are
HIGH by default and LOW when 10K Ω Pull down is attached.
I/O MODE CONFIGURATION
MODE
1 (OUTPUT)
0 (INPUT)
PIN15
BCLK5
PCISTP
PIN46
REF1
CPUSTP
45437 Warm Springs Blvd., Fremont, California 94539, TEL 510-492-0990 FAX 510-492-0991
9704.Rev.1C Page 1
1 page 5. BYTE4: SDRAM Clock Register (1=enable, 0=disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN #
N/A
N/A
N/A
N/A
17
18
20
21
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
6. BYTE5: Peripheral Clock Register (1=enable, 0=disable)
BIT
PIN #
DESCRIPTION
Bit 7 N/A Reserved
Bit 6 N/A Reserved
Bit 5 N/A Reserved
Bit 4 47 IOAPIC (Active/Inactive)
Bit 3 N/A Reserved
Bit 2 N/A Reserved
Bit 1 46 REF1 (Active/Inactive)
7. BYTE6: Optional Register (1=enable, 0=disable)
BIT
PIN #
DESCRIPTION
Bit 7 N/A Reserved
Bit 6 N/A Reserved
Bit 5 N/A Reserved
Bit 4 N/A Reserved
Bit 3 N/A Reserved
Bit 2 N/A Reserved
Bit 1 N/A Reserved
Bit 0 N/A Reserved
Notes: 1. Inactive means outputs are STOPPED and held LOW.
45437 Warm Springs Blvd., Fremont, California 94539, TEL 510-492-0990 FAX 510-492-0991
9704.Rev.1C Page 5
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet PLL52C63-01.PDF ] |
Número de pieza | Descripción | Fabricantes |
PLL52C63-01 | Pentium/SDRAM Clock Generator | PhaseLink |
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