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PDF RTL8201N-GR Data sheet ( Hoja de datos )
| Número de pieza | RTL8201N-GR | |
| Descripción | SINGLE-CHIP/PORT 10/100M FAST ETHERNET PHYCEIVER | |
| Fabricantes | REALTEK | |
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RTL8201N-GR
SINGLE-CHIP/PORT
10/100M FAST ETHERNET PHYCEIVER
WITH AUTO MDIX
DATASHEET
Rev. 1.1
22 August 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
1 page  
RTL8201N
Datasheet
List of Tables
Table 1. MII Interface..................................................................................................................................5
Table 2. SNI (Serial Network Interface) 10Mbps Only ..............................................................................6
Table 3. Clock Interface ..............................................................................................................................6
Table 4. 10Mbps/100Mbps Network Interface............................................................................................7
Table 5. Device Configuration Interface .....................................................................................................7
Table 6. LED Interface/PHY Address Configuration..................................................................................8
Table 7. Power Pins .....................................................................................................................................8
Table 8. Reset and Other Pins......................................................................................................................8
Table 9. Register 0 Basic Mode Control Register .......................................................................................9
Table 10. Register 1 Basic Mode Status Register........................................................................................10
Table 11. Register 2 PHY Identifier Register 1...........................................................................................11
Table 12. Register 3 PHY Identifier Register 2...........................................................................................11
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)..................................................11
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) ....................................12
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) .........................................................13
Table 16. Register 16 NWay Setup Register (NSR)....................................................................................13
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) ..............................13
Table 18. Register 18 RX_ER Counter (REC)............................................................................................14
Table 19. Register 19 SNR Display Register ..............................................................................................14
Table 20. Register 25 Test Register.............................................................................................................14
Table 21. Serial Management ......................................................................................................................16
Table 22. Setting the Medium Type and Interface Mode to MAC..............................................................17
Table 23. UTP Mode and MII Interface ......................................................................................................18
Table 24. UTP Mode and SNI Interface......................................................................................................18
Table 25. Fiber Mode and MII Interface .....................................................................................................18
Table 26. Auto-Negotiation Mode Pin Settings ..........................................................................................19
Table 27. Power Saving Mode Pin Settings ................................................................................................20
Table 28. Absolute Maximum Ratings........................................................................................................24
Table 29. Operating Conditions...................................................................................................................24
Table 30. Power Dissipation........................................................................................................................24
Table 31. Input Voltage: Vcc.......................................................................................................................25
Table 32. MII Transmission Cycle Timing .................................................................................................26
Table 33. MII Reception Cycle Timing.......................................................................................................27
Table 34. SNI Transmission Cycle Timing .................................................................................................28
Table 35. SNI Reception Cycle Timing ......................................................................................................29
Table 36. MDC/MDIO Timing....................................................................................................................30
Table 37. Crystal Characteristics.................................................................................................................31
Table 38. Transformer Characteristics ........................................................................................................31
Table 39. Ordering Information...................................................................................................................33
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
v
Rev. 1.1
5 Page 
6. Pin Descriptions
LI: Latched Input during Power up or Reset
IO: Bi-directional input and output
O: Output
P: Power
RTL8201N
Datasheet
I: Input
6.1. MII Interface
Name
TXC
Type
O
TXEN
I
TXD[3:0] I
RXC
O
COL/
LI/O
CONFIG[6]
CRS/
LI/O
CONFIG[5]
RXDV/
RMII
LI/O
RXD[3:0] O
Pin No.
24
29
28, 27, 26, 25
22
46
47
16
21, 20, 19, 17
Table 1. MII Interface
Description
Transmit Clock.
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0]. An
internal weak pull low resistor to prevent the bus floating.
Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is
asserted. An internal weak pull high resistor prevents the bus floating.
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3]
signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
Collision Detect.
COL is asserted high when a collision is detected on the media.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: SNI mode
1: MII mode
This pin can be directly connected to GND or VCC.
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
During power on reset, this pin set high to put the RTL8201N into repeater
mode. This pin can be directly connected to GND or VCC.
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on the
rising edge of the RXC.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: MII mode
1: RMII mode
This pin can be directly connected to GND or VCC.
Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
5
Rev. 1.1
11 Page | ||
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