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PDF ML610Q479 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q479 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML610Q477/ML610Q478/ML610Q479
8-bit Microcontroller with a Built-in LCD driver
FEDL610Q479-03
Issue Date:Jul.31, 2014
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as the UART, RC oscillation type A/D converter, and LCD driver.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version can rewrite programs on-board, which can contribute to reduction in product development TAT. The flash
memory incorporated into this MTP version implements the mask ROM-equivalent low-voltage operation (1.25V or higher)
and low-power consumption (typically 5uA at low-speed operation), enabling volume production by the MTP version. For
industrial use, ML610Q477P/ML610Q478P/ML610Q479P with the extended operating ambient temperature ranging from
-40°C to 85°C are available.
FEATURES
• CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- On-Chip debug function
- Minimum instruction execution time
30.5 µs (@ 32.768 kHz system clock)
2 µs (@ 500 kHz system clock)
0.5 µs (@ 2 MHz system clock)
• Internal memory
- Internal 24KByte flash memory (12K x 16 bits) (including unusable 1K Byte TEST area)
- Internal 2KByte RAM (2048 x 8 bits)
• Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 25 maskable interrupt sources:
Internal source: 13 (Timer0, Timer1, Timer 2, Timer 3, Timer C, Timer D, UART0, RC A/D converter, TBC128Hz,
TBC32Hz, TBC16Hz, TBC2Hz, Analog Comparator)
External source: 12 (P00, P01, P02, P03, P50, P51, P52, P53, P54, P55, P56, P57)
(One interrupt request is generated from P50 to P57 interrupt sources.)
• Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
• Watchdog timer
- Non-maskable interrupt and reset
- Free running
- Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
1 page  
FEDL610Q479-03
ML610Q477/ML610Q478/ML610Q479
BLOCK DIAGRAM
Block Diagram of ML610Q477/ML610Q478/ML610Q479
CPU (nX-U8/100)
EPSW1−3
PSW
GREG
0−15
ELR1−3
LR
ECSR1−3
DSR/CSR
Timing
Controller
On-Chip
ICE
ALU
Instruction
Decoder
EA
SP
Instruction
Register
PC
BUS
Controller
Data-bus
VSS
RESET_N
TEST0
RESET &
TEST
RAM
2K byte
Program
Memory
(Flash)
24Kbyte
XT0
XT1
LSCLK*
OSC
VDD
VDDL
VDDX
CH1, CH2
RCM*
IN1*
CS1*
RS1*
RT1*
CMPP0*
CMPM0*
CMPP1*
CMPM1*
Power
RC-ADC
INT
1
INT
1
Analog
Comparator
Interrupt
Controller
INT
1 WDT
INT
4 TBC
Capture
×2
INT
6 8bit Timer
×6
Display
register
190bit
INT
1
UART
INT
5
GPIO
LCD
Driver
LCD
BIAS
VPP
RXD0*
TXD0*
P00 to P03
P20, P21
P35
P42 to P47
P50 to P57
P60 to P67 (ML610Q477)
P60 to P63 (ML610Q478)
COM0 to COM4 (*1)(*2)(*3)
SEG0 to SEG29 (ML610Q477) (*1)
SEG0 to SEG33 (ML610Q478) (*2)
SEG0 to SEG37 (ML610Q479) (*3)
VL1, VL2, VL3
C1, C2
* Secondary function or Tertiary function
(*1) Select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3 commons, and 30
segments x 2 commons with the register
(*2) Select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3 commons, and 34
segments x 2 commons with the register
(*3) Select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3 commons, and 38
segments x 2 commons with the register
Figure 1 ML610Q477/ML610Q478/ML610Q479 Block Diagram
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5 Page 
FEDL610Q479-03
ML610Q477/ML610Q478/ML610Q479
PIN PAD
No. No.
68 66
67 65
44
33
22
11
Pin name
P52/EXI8
P53/EXI8
P54/EXI8/
CMPP0
P55/EXI8/
CMPP1
P56/EXI8/
CMPM0
P57/EXI8/
CMPM1
Primary function
I/O Function
I/O Input/output port, External interrupt
I/O Input/output port, External interrupt
Input/output port, External interrupt
I/O Analog comparator noninverting
input0 pin
Pin name
⎯
⎯
⎯
Secondary function
I/O Function
⎯⎯
⎯⎯
⎯⎯
Input/output port, External interrupt
I/O Analog comparator noninverting
input1 pin
Input/output port, External interrupt
I/O Analog comparator inverting
input0 pin
Input/output port, External interrupt
I/O Analog comparator inverting
input1 pin
⎯
⎯
⎯
⎯⎯
⎯⎯
⎯⎯
11/31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML610Q479.PDF ] | |
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