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Número de pieza | AT25256B | |
Descripción | SPI Serial EEPROM | |
Fabricantes | ATMEL Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AT25256B (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
No Preview Available ! AT25128B and AT25256B
SPI Serial EEPROM
128K (16,384 x 8), 256K (32,768 x 8)
DATASHEET
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
̶ Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
̶ VCC = 1.8V to 5.5V
20MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
̶ Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and
Software Data Protection
Self-timed Write Cycle (5ms max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Green (Pb/Halogen-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT25128B/256B provides 131,072/262,144 bits of Serial Electrically
Erasable Programmable Read-Only Memory (EEPROM) organized as
16,384/32,768 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operation are essential. The AT25128B/256B is available in space saving JEDEC
SOIC, TSSOP, UDFN, and VFBGA packages.
The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed
via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block Write protection is enabled by programming the status register with one of
four blocks of Write Protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware Data Protection
is provided via the WP pin to protect against inadvertent write attempts. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
1 page 4.3 AC Characteristics
Table 4-3. AC Characteristics
Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max Units
fSCK SCK Clock Frequency
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
20
10 MHz
5
tRI Input Rise Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
2
2 μs
2
tFI Input Fall Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
2
2 μs
2
tWH SCK High Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
20
40
80
ns
tWL SCK Low Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
20
40
80
ns
tCS CS High Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
100
100
200
ns
tCSS CS Setup Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
100
100
200
ns
tCSH CS Hold Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
100
100
200
ns
tSU Data In Setup Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
ns
tH Data In Hold Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
ns
tHD Hold Setup Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
ns
tCD Hold Hold Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
5
10
20
ns
tV Output Valid
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
20
40 ns
80
tHO Output Hold Time
4.5 – 5.5
2.5 – 5.5
1.8 – 5.5
0
0
0
ns
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
5
5 Page 7. Timing Diagrams — SPI Mode 0 (0,0)
Figure 7-1. Synchronous Data Timing (for Mode 0)
VIH
CS
VIL
tCSS
SCK
VIH
VIL
VIH
SI
VIL
tWH
tSU tH
Valid In
VOH
SO
VOL
HI-Z
tWL
tV
Figure 7-2. WREN Timing
CS
SCK
SI
SO
WREN Opcode
HI-Z
Figure 7-3. WRDI Timing
CS
SCK
SI
SO
WRDI Opcode
HI-Z
tCS
tCSH
tHO tDIS
HI-Z
AT25128B/256B [DATASHEET]
Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015
11
11 Page |
Páginas | Total 22 Páginas | |
PDF Descargar | [ Datasheet AT25256B.PDF ] |
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