PDF SH6883 Data sheet ( Hoja de datos )

Número de pieza	SH6883
Descripción	Low Speed USB Micro-controller
Fabricantes	Sino Wealth
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No Preview Available ! SH6883 Low Speed USB Micro-controller Features CMOS technology for low power consumption Operating voltage: 4.4V to 5.25V 3.3V regulator output. Built-in 1.5K ohm USB pull-up resistor 8-bit CMOS Micro-Processor (uP) core - Instruction set is compatible with standard 8051 - Operation frequency: 6MHz (with external ceramic resonator) Two 8-Bit auto-reloadable Base Timer Interrupts - 11 vectors interrupt structure - Two programmable priority levels 256 Bytes Internal DATA Memory USB Specification Compliance - Complies with Universal Serial Bus specification 1.1 - Support one Low-Speed USB Device Address with 3 endpoints (endpoint 0, 1, and 2) One set of Time Capture circuit (rising and falling edge) 8K Bytes Program Memory (Mask ROM) Two Blue LED ports Build-in internal 32KHz oscillator for programmable Wake-up Timer General Purpose I/O. Up to 37 Selectable GPIO on 48-pin LQFP package Reset - Hardware Reset (External Reset, Power-on reset and Low-Voltage Reset) - USB Reset - Watch-dog Reset - Resume Reset Package - 20-pin SSOP - 48-pin LQFP General Description The SH6883 is designed for high performance Low-speed USB devices. It contains an 8051 micro-controller, Low-Speed USB SIE, Transceiver and data FIFO, build-in 3.3V regulator, on-chip 8K bytes Mask ROM and internal 256 bytes data RAM, Time capture circuit, Base timer, programmable Watch-dog timer and Wake-up timer, 37 Selectable GPIO (on 48-pin LQFP package), support multiple type LED driving capability for different application, build-in internal 32KHz oscillator, POR and LVR circuit saving your external components cost. Applications can cover such items as keyboards, mice and others. 1 V1.0 1 page SH6883 Functional Description 1. Memory 1.1. Memory Allocation There are 8K bytes Program Memory and 256-byte Data Memory. For the detailed information, please refer to FIG. 1-1. Program Memory (Mask ROM) 0xFF Data Memory (Internal SRAM) 0x1FFF Upper 128 Bytes (Indirect Addressing Only) Special Function Register Areas (Direct Addressing Only) 8K Bytes Mask ROM for User's Code Segment 0x0000 0x80 0x7F Direct and Indirect Addressing Areas 0x20 0x1F 0x00 General Purpose Registers Low 128 Bytes Direct and Indirect Addressing Areas FIG. 1-1 SH6883 Program/Data Memory Map 1.2. Program Memory 8K Bytes (0000h - 1FFFH) on-chip program memory for user codes. 1.3. Data Memory Internal RAM: There are totally 256 bytes internal DATA Memory in the uP. Internal Special Function Registers (SFR): There are 128 bytes SFR, which is the internal reserved memory for system registers in the uP. 1.4. Registers System Registers Address Name Init. R/W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00E0H 00F0H 00D0H 0081H 0082H 0083H ACC B PSW SP DPL DPH 00H R/W 00H R/W 00H R/W 07H R/W 00H R/W 00H R/W Address Name Init. R/W 0087H PCON 00000000B R/W 008EH SUSLO 00H R/W ACC.7 ACC.6 ACC.5 ACC.4 B.7 B.6 B.5 B.4 CY AC F0 RS1 SP7 SP6 SP5 SP4 DPL7 DPL6 DPL5 DPL4 DPH7 DPH6 DPH5 DPH4 Idle and Power-down Control Registers Bit7 Bit6 Bit5 Bit4 00 0 0 SUSL7 SUSL6 SUSL5 SUSL4 ACC.3 B.3 RS0 SP3 DPL3 DPH3 Bit3 0 SUSL3 ACC.2 B.2 OV SP2 DPL2 DPH2 Bit2 0 SUSL2 ACC.1 B.1 0 SP1 DPL1 DPH1 Bit1 PD SUSL1 ACC.0 B.0 P SP0 DPL0 DPH0 Bit0 IDL SUSL0 00AFH PRCON 00000001B R/W 0 0 0 0 General I/O Ports Registers Address Name Init. R/W Bit7 Bit6 Bit5 Bit4 0 ENWDT 0 ENLVR Bit3 Bit2 Bit1 Bit0 0080H 0090H 00A0H 00B0H 00C0H 00A2H 00A3H 00A4H 00A5H 00A6H P0 P1 P2 P3 P4 P0WK P1WK P2WK P3WK P4WK 11111111B 11111111B 11111111B 11111111B 01111111B 00000000B 00000000B 00000000B 00000000B 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P0.7 P1.7 P2.7 P3.7 0 P0WK7 P1WK7 P2WK7 P3WK7 0 P0.6 P1.6 P2.6 P3.6 P4.6 P0WK6 P1WK6 P2WK6 P3WK6 P4WK6 P0.5 P1.5 P2.5 P3.5 P4.5 P0WK5 P1WK5 P2WK5 P3WK5 P4WK5 P0.4 P1.4 P2.4 P3.4 0 P0WK4 P1WK4 P2WK4 P3WK4 0 P0.3 P1.3 P2.3 P3.3 0 P0WK3 P1WK3 P2WK3 P3WK3 0 P0.2 P1.2 P2.2 P3.2 P4.2 P0WK2 P1WK2 P2WK2 P3WK2 0 P0.1 P1.1 P2.1 P3.1 P4.1 P0WK1 P1WK1 P2WK1 P3WK1 0 P0.0 P1.0 P2.0 P3.0 P4.0 P0WK0 P1WK0 P2WK0 P3WK0 0 009AH 009BH 009CH P0CON 00000000B R/W P0CON7 P1CON 00000000B R/W P1CON7 P2CON 00000000B R/W P2CON7 P0CON6 P1CON6 P2CON6 P0CON5 P1CON5 P2CON5 P0CON4 P1CON4 P2CON4 P0CON3 P1CON3 P2CON3 P0CON2 P1CON2 P2CON2 P0CON1 P0CON0 P1CON1 P1CON0 P2CON1 P2CON0 009DH 009EH 00ADH P3CON 00000000B R/W P3CON7 P4CON 01100000B R/W 0 P3SEL 00000000B R/W P3SEL7 P3CON6 P4CON6 P3SEL6 P3CON5 P4CON5 0 P3CON4 0 0 P3CON3 0 0 P3CON2 P4CON2 0 P3CON1 P3CON0 P4CON1 P4CON0 00 5 5 Page Instruction Set List (continued) RL RLC RR RRC SWAP A A A A A MOV MOVC MOVX PUSH POP XCH XCHD Opcode A, Rn A, @Ri Rn, A @Ri, A A, direct A, #data Rn, #data direct, A direct, Rn @Ri, #data Rn, direct direct, @Ri @Ri, direct direct, direct direct, #data DPTR, #data16 A, @A+DPTR A, @A+PC @Ri, A A, @Ri @DPTR, A A, @DPTR direct direct A, Rn A, @Ri A, direct A, @Ri CLR SETB CPL ANL ORL MOV Opcode C bit C bit C bit C, bit C, /bit C, bit C, /bit C, bit bit, C SH6883 1 1 Rotate acc left 1 1 Rotate acc left through the carry 1 1 Rotate acc right 1 1 Rotate acc right throught the carry 1 4 Swap nibbles within the acc Data Transfer Bytes Cycles Meaning 1 1 Move reg to acc 1 2 Move indir byte to acc 1 2 Move acc to reg 1 2 Move acc to indir byte 2 2 Move dir byte to acc 2 2 Move imm. Data to acc 2 2 Move imm. Data to reg 2 2 Move acc to dir byte 2 2 Move reg to dir byte 2 2 Move imm. Data to indir byte 2 3 Move dir byte to reg 2 3 Move indir byte to dir byte 2 3 Move dir byte to indir byte 3 3 Move dir byte to dir byte 3 3 Move imm. Data to dir byte 3 3 Load data pointer with 16-bit constant 1 7 Move code byte relative to DPTR to acc 1 8 Move code byte relative to PC to acc 1 4 Move acc to xdata byte (8 bit address) 1 5 Move xdata byte to acc (8 bit address) 1 5 Move acc to xdata byte (16 bit address) 1 6 Move xdata byte to acc (16 bit address) 2 5 Push dir byte to stack 2 4 Pop dir byte from stack 1 3 Exchange reg with acc 1 4 Exchange indir byte with acc 2 4 Exchange dir byte with acc 1 4 Exchange low-order digit in indir byte with acc Bit Manipulation Bytes Cycles Meaning 1 1 Clear carry 2 3 Clear dir bit 1 1 Set carry 2 3 Set dir bit 1 1 Complement carry 2 2 Complement dir bit 2 2 AND dir bit to carry 2 2 AND complement of dir bit to carry 2 2 OR dir bit to carry 2 2 OR complement of dir bit to carry 2 2 Move dir bit to carry 2 2 Move carry to dir bit 11 11 Page

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