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PDF ST7032i Data sheet ( Hoja de datos )
| Número de pieza | ST7032i | |
| Descripción | Dot Matrix LCD Controller/Driver | |
| Fabricantes | Sitronix | |
| Logotipo |  |
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Sitronix
ST
ST7032
Dot Matrix LCD Controller/Driver
n Features
l 5 x 8 dot matrix possible
l Low power operation support:
-- 2.7 to 5.5V
l Range of LCD driver power
-- 3.0 to 7.0V
l 4-bit, 8-bit, serial MPU or 400kbits/s fast
I2C-bus interface are available
l 80 x 8-bit display RAM (80 characters max.)
l 10,240-bit character generator ROM for a
total of 256 character fonts(max)
l 64 x 8-bit character generator RAM(max)
l 16-common x 80-segment and 1-common x
80-segment ICON liquid crystal display
driver
l 16 x 5 – bit ICON RAM(max)
l Wide range of instruction functions:
Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift, double height font
l Automatic reset circuit that initializes the
controller/driver after power on and external
reset pin
l Internal oscillator(Frequency=540KHz) and
external clock
l Built-in voltage booster and follower circuit
(low power consumption )
l Com/Seg direction selectable
l Multi-selectable for CGRAM/CGROM size
l Instruction compatible to ST7066U
l Available in COG type
n Description
The ST7032 dot-matrix liquid crystal display controller can
display alphanumeric, Japanese kana characters, and
symbols. It can be configured to drive a dot-matrix liquid
crystal display under the control of a 4 / 8-bit with
6800-series or 8080-series, 3/4-line serial interface
microprocessor. Since all the functions such as display
RAM, character generator ROM/RAM and liquid crystal
driver, required for driving a dot-matrix liquid crystal display
are internally provided on one chip, a minimal system can
be used with this controller/driver.
The ST7032 is suitable for low voltage supply 2.7V to 5.5V)
and is perfectly suitable for any portable product which is
driven by the battery and requires low power consumption.
The ST7032 LCD driver consists of 17 common signal
drivers and 80 segment signal drivers. The maximum
display RAM size can be either 80 characters in 1-line
display or 40 characters in 2-line display. A single ST7032
can display up to one 16-character line or two 16-character
lines.
The ST7038 character generator ROM size is 256 5x8dot
bits which can be used to generate 256 different character
fonts (5x8dot).
The ST7032 dot-matrix LCD driver does not need extra
cascaded drivers.
Product Name
ST7032-0D
Character generator
ROM Size
256
OPR1 OPR2 Support Character
1 1 English/Japan/European
ST7032
6800-4bit / 8bit interface
(without IIC interface)
ST7032i
IIC interface
V1.2
1/62
2005/10/17
1 page  
ST7032
Pad No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Function
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
X
-1386.5
-1324.5
-1262.5
-1200.5
-1138.5
-1076.5
-1014.5
-952.5
-890.5
-828.5
-766.5
-704.5
-642.5
-580.5
-518.5
-456.5
-394.5
-332.5
-270.5
-208.5
-146.5
-84.5
-22.5
39.5
101.5
163.5
225.5
287.5
349.5
411.5
473.5
535.5
597.5
659.5
721.5
783.5
845.5
907.5
969.5
1031.5
Y
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
Pad No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Function
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
COM[9]
COM[10]
COM[11]
COM[12]
COM[13]
COM[14]
COM[15]
COM[16]
COMI2
X
1093.5
1155.5
1217.5
1279.5
1341.5
1403.5
1465.5
1527.5
1589.5
1651.5
1713.5
1775.5
1837.5
1899.5
1961.5
2023.5
2085.5
2147.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
Y
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-383
-321
-259
-197
-135
-73
-11
51
113
175
237
299
361
423
V1.2
5/62
2005/10/17
5 Page 
ST7032
·Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
·Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to
do so and the message is not corrupted
·Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Acknowledge is not Busy Flag in I2C interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I2C Interface is illustrated in Fig.4.
SDA
SCL
data line
change
stable;
of data
data valid allowed
Figure 1. Bit transfer
SDA
SCL
SP
START con dition
STOP con dition
Figure 2. Definition of START and STOP conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Figure 3. System configuration
V1.2
11/62
2005/10/17
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST7032i.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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