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PDF PSD813F1-A Data sheet ( Hoja de datos )
| Número de pieza | PSD813F1-A | |
| Descripción | Flash In-System Programmable (ISP) Peripherals | |
| Fabricantes | STMicroelectronics | |
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PSD813F1-A
Flash In-System Programmable (ISP) Peripherals
For 8-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD813F1-A
– 3.3 V±10% for PSD813F1-AV
s Up to 1Mbit of Primary Flash Memory (8 uniform
sectors)
s 256Kbit Secondary EEPROM (4 uniform
sectors)
s Up to 16Kbit SRAM
s Over 3,000 Gates of PLD: DPLD and CPLD
s 27 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
Figure 1. Packages
PQFP52 (T)
PLCC52 (K)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/3
1 page  
Preliminary
1.0
Introduction
Programmable Peripheral
Revision A Flash PSD
PSD813F1-A
Flash In-System-Programmable
Microcontroller Peripherals
The PSD813F1 family of Programmable Microcontroller (MCU) Peripherals brings
In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a
simple and flexible solution for embedded designs. PSD813F1 devices combine many of
the peripheral functions found in MCU based applications:
• 1 Mbit of Flash memory
• A second EEPROM memory
• Over 3,000 gates of Flash programmable logic
• SRAM
• Reconfigurable I/O ports
• Programmable power management.
PSD813F1 devices integrate an optimized “microcontroller macrocell” logic architecture
called the Micro⇔CellTM. The Micro⇔Cell was created to address the unique requirements
of embedded system designs. It allows direct connection between the system address/data
bus and the internal PSD registers to simplify communication between the MCU and other
supporting devices.
1
5 Page 
Preliminary
PSD813F1
Architectural
Overview
(cont.)
PSD813F1-A
5.4 I/O Ports
The PSD813F1 has 27 I/O pins divided among four ports (Port A, B, C, and D). Each
I/O pin can be individually configured for different functions. Ports A, B, C and D can be
configured as standard MCU I/O ports, PLD I/O, or latched address outputs for
microcontrollers using multiplexed address/data busses.
The JTAG pins can be enabled on Port C for In-System Programming (ISP).
Ports A and B can also be configured as a data port for a non-multiplexed bus or
multiplexed Address/Data buses for certain types of 16-bit microcontrollers.
5.5 Microcontroller Bus Interface
The PSD813F1 easily interfaces with most 8-bit microcontrollers that have either
multiplexed or non-multiplexed address/data busses. The device is configured to respond to
the microcontroller’s control signals, which are also used as inputs to the PLDs. Where
there is a requirement to use a 16-bit data bus to interface to a 16-bit microcontroller, two
PSDs must be used. Section 9.3.5 contains microcontroller interface examples.
5.6 JTAG Port
In-System Programming can be performed through the JTAG pins on Port C. This serial
interface allows complete programming of the entire PSD813F1 device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port C. Table 3 indicates the JTAG signals pin
assignments.
Table 3. JTAG Signals on Port C
Port C Pins
JTAG Signal
PC0 TMS
PC1 TCK
PC3 TSTAT
PC4 TERR
PC5 TDI
PC6 TDO
7
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