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PDF CM1215 Data sheet ( Hoja de datos )
| Número de pieza | CM1215 | |
| Descripción | Low Capacitance ESD Arrays | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CM1215
1, 2 and 4-Channel
Low Capacitance
ESD Arrays
Product Description
The CM1215 family of diode arrays provides ESD protection for
electronic components or sub−systems requiring minimal capacitive
loading. These devices are ideal for protecting systems with high data
and clock rates or for circuits requiring low capacitive loading. Each
ESD channel consists of a pair of diodes in series which steer the
positive or negative ESD current pulse to either the positive (VP) or
negative (VN) supply rail. The CM1215 protects against ESD pulses
up to ±15 kV per the IEC 61000−4−2 standard.
This device is particularly well−suited for protecting systems using
high−speed ports such as USB2.0, IEEE1394 (Firewire®, iLinkt),
Serial ATA, DVI, HDMI and corresponding ports in removable
storage, digital camcorders, DVD−RW drives and other applications
where extremely low loading capacitance with ESD protection are
required in a small package footprint.
Features
• One, two, and four channels of ESD Protection
• Provides ±15 kV ESD Protection on Each Channel Per the IEC
61000−4−2 ESD Requirements
• Channel Loading Capacitance of 1.6 pF Typical
• Channel I/O to GND Capacitance Difference of 0.04 pF Typical
• Mutual Capacitance of 0.13 pF Typical
• Minimal Capacitance Change with Temperature and Voltage
• Each I/O Pin Can Withstand Over 1000 ESD Strikes
• SOT Packages
• These Devices are Pb−Free and are RoHS Compliant
Applications
• IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps
• DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,
LCD Displays
• Serial ATA Ports in Desktop PCs and Hard Disk Drives
• PCI Express Ports
• General Purpose High−Speed Data Line ESD Protection
http://onsemi.com
SOT23−3
SO SUFFIX
CASE 419AH
SOT143
SR SUFFIX
CASE 527AF
SOT23−5
SO SUFFIX
CASE 527AH
SOT23−6
SO SUFFIX
CASE 527AJ
MARKING DIAGRAM
E151 MG
G
1
E152 MG
G
E153 MG
G
1
E154 MG
G
1
XXXX = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
CM1215−01SO
Package
SOT23−3
(Pb−Free)
Shipping†
3000/Tape & Reel
CM1215−02SR SOT143 3000/Tape & Reel
(Pb−Free)
CM1215−02SO
CM1215−04SO
SOT23−5
(Pb−Free)
SOT23−6
(Pb−Free)
3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 3
1
Publication Order Number:
CM1215/D
1 page  
CM1215
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking
an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on
the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be
approximated by d(ESD)/dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
L1 POSITIVE SUPPLY
PATH OF ESD CURRENT
PULSE (IESD)
D1
C1
ONE
CHANNEL
D2
LINE BEING
PROTECTED
CHANNEL
IMPUT
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
GROUND RAIL
CHASSI‘S GROUND
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
http://onsemi.com
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CM1215.PDF ] | |
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