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PDF SGN6210 Data sheet ( Hoja de datos )
| Número de pieza | SGN6210 | |
| Descripción | RF Transceiver/Framer | |
| Fabricantes | Signia | |
| Logotipo |  |
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Product Description:
The Signia SGN6210 IC is a low-cost, fully integrated CMOS
radio frequency (RF) transceiver block, combined with a 64-
byte buffered framer block. In normal applications, the
SGN6210 is connected to a low-cost microcomputer (MCU).
The on-chip framer processes and stores the RF data in the
background, unloading this critical timing function from the
MCU. This lowers MCU speed requirements, expedites
product development time, and frees the MCU for
implementing additional product features.
The RF transceiver block is a self-contained, fast-hopping
GFSK data modem, optimized for use in the widely available
2.4 GHz ISM band. It contains transmit, receive, VCO and PLL
functions, including an on-chip channel filter and resonator,
thus minimizing the need for external components. The
receiver utilizes extensive digital processing for excellent
overall performance, even in the presence of interference and
transmitter impairments. Transmit power is digitally controlled.
The low-IF receiver architecture results in sensitivity
to -80 dBm or better, with impressive selectivity.
The framer register settings determine the over-the-air
formatting characteristics. Transmit data is easily sent over-
the-air as a complete frame of data, with preamble, address,
payload, and CRC. Receiving data is just the opposite, using
the preamble to train the receiver clock recovery, then the
address is checked, then the data is reverse formatted for
receive, followed by CRC. All of this is done in hardware to
ease the programming and overhead requirements of the
baseband MCU.
For longer battery life, power consumption is minimized by
automatic enabling of the various transmit, receive, PLL, and
PA sections, depending on the instantaneous state of the chip.
A sleep mode is also provided for ultra low current
consumption.
This product is supplied in lead-free, RoHS compliant, 24-lead
4x4 mm JEDEC standard QFN package, featuring an exposed
pad on the bottom for best RF characteristics.
Ordering Information
SGN6210
RF Transceiver/Framer
Signia Technologies Co., Ltd.
7F., No.68, Sec. 3, Nanjing E. Rd., (Tel) 886-02-2515-1956
Jhongshan District,
(Fax) 886-02-2515-1963
Taipei City 104, Taiwan
SGN6210
RF Transceiver/Framer
Production Data Sheet
Key Features:
• Combines 2.4 GHz GFSK RF transceiver with
8-bit data framer function
• Eliminates need for external software or
hardware FIFO; offloads MCU for other tasks
• Simple microprocessor interface – 4 wires for
SPI, plus 3 wires for RST/buffer control
• Flexible architecture with 64 byte transmit,
receive buffers allow short, long, or infinite
packet length
• Always 1 Mbps over-the-air symbol rate,
regardless of MCU speed or architecture
• Preamble can be 1 to 8 bytes
• Supports 1, 2, 3, or 4 word address (up to 64
bits)
• Various Payload data formats to eliminate DC
offset, enhance receive clock recovery and BER
• Programmable data whitening
• Supports Forward Error Correction (FEC):
none, 1/3, or 2/3
• Supports 16-bit CRC
• Power management for minimizing current
consumption
• Lead-free 4x4mm QFN package
with minimum RF parasitics
Applications:
• Wireless devices that need quick time-to-market
• Battery Powered wireless devices
• Wireless streaming audio
• Home and factory automation
• Simple and fast wireless data networks
• Cordless headsets and Cellular Phones
• Wireless voice and VOIP
• Wireless security and access control
August 2007
SGN6210 Data Sheet
www.signiatech.com
Page 1 of 13
1 page  
SGN6210
Parameter
RF VCO and PLL Section
Typical PLL lock range
Tx, Rx Frequency Tolerance
Channel (Step) Size
SSB Phase Noise
Crystal oscillator freq. range
(Reference Frequency)
Crystal oscillator
digital trim range, typ.
RF PLL Settling Time
Spurious Emissions
LDO Voltage Regulator
Section
Dropout Voltage
Quiescent current
Symbol
Specification
Units
MIN TYP MAX
Test Condition and Notes
FLOCK
THOP
OBS_1
OBS_2
2366
--
1
-95
-115
12
2516
MHz
ppm
MHz
dBc/Hz
dBc/Hz
MHz
Same as XTAL pins frequency tolerance
550kHz offset
2MHz offset
Designed for 12 MHz crystal reference freq.
-5 +5 ppm
75
< -75
-68
150
-57
-47
uS
dBm
dBm
Settle to within 30 kHz of final value.
30 MHz ~ 1 GHz
1 GHz ~ 12.75 GHz
IDLE state,
Synthesizer and
VCO ON.
Vdo 0.5 V Measured during Receive state
Iq 8 uA No-load current consumed by LDO reg.
August 2007
SGN6210 Data Sheet
www.signiatech.com
Page 5 of 13
5 Page 
Package Outline
QFN 24 Lead Exposed Pad Package, 4x4 mm, 0.5mm pitch. Dimensions in mm.
SGN6210
Dim.
A
A1
A3
b
D/E
D2/E2
e
Min.
0.70
0
0.18
3.90
1.90
Nom.
0.75
0.02
0.203 REF
0.25
4.00
2.00
0.50 BSC
Max.
0.80
0.05
0.30
4.10
2.10
Dim.
L
y
Min.
0.30
Nom.
0.40
0.08
Max.
0.50
August 2007
SGN6210 Data Sheet
www.signiatech.com
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SGN6210.PDF ] | |
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