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Número de pieza | M24C64-A125 | |
Descripción | Automotive 64-Kbit serial I2C bus EEPROM | |
Fabricantes | STMicroelectronics | |
Logotipo | ||
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No Preview Available ! M24C64-A125
Automotive 64-Kbit serial I²C bus EEPROM with 1 MHz clock
TSSOP8 (DW)
169 mil width
SO8 (MN)
150 mil width
WFDFPN8 (MF)
2 x 3 mm
Datasheet - production data
Features
• Compatible with all I2C bus modes
– 1 MHz
– 400 kHz
– 100 kHz
• Memory array
– 64 Kbit (8 Kbyte) of EEPROM
– Page size: 32 byte
– Additional Write lockable page
(Identification page)
• Extended temperature and voltage ranges
– -40 °C to 125 °C; 1.7 V to 5.5 V
• Schmitt trigger inputs for noise filtering.
• Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
• Data retention
– 50 years at 125 °C
– 100 years at 25 °C
• ESD protection (Human Body Model)
– 4000 V
• Packages
– RoHS compliant and halogen-free
(ECOPACK2®)
February 2016
This is information on a product in full production.
DocID023023 Rev 9
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1 page M24C64-A125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC =
Maximum Rbus value versus bus
400 kHz
parasitic
..........
capacitance
.....
Cbus)
.....
for an
...
I2C
.
.
.
.
.
.
.
.
.
.
.
.
.
.
31
bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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5 Page M24C64-A125
Device operation
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
3.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet M24C64-A125.PDF ] |
Número de pieza | Descripción | Fabricantes |
M24C64-A125 | Automotive 64-Kbit serial I2C bus EEPROM | STMicroelectronics |
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