PDF ISL71831SEH Data sheet ( Hoja de datos )

Número de pieza	ISL71831SEH
Descripción	Radiation Hardened 5V 32-Channel Analog Multiplexer
Fabricantes	Intersil
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No Preview Available ! DATASHEET Radiation Hardened 5V 32-Channel Analog Multiplexer ISL71831SEH The ISL71831SEH is a radiation tolerant, 32-channel multiplexer that is fabricated using Intersil’s proprietary P6-SOI process technology to provide excellent latch-up performance. It operates with a single supply range from 3V to 5.5V and has a 5-bit address line plus an enable that can be driven with adjustable logic thresholds to conveniently select one of 32 available channels. An inactive channel is separated from the active channel by a high impedance, which inhibits any interaction between them. The ISL71831SEH’s low rDS(ON) allows for improved signal integrity and reduced power losses. The ISL71831SEH is also designed for cold sparing making it excellent for redundancy in high reliability applications. It is designed to provide a high impedance to the analog source in a powered off condition, making it easy to add additional backup devices without incurring extra power dissipation. The ISL71831SEH also has analog overvoltage protection on the input that disables the switch during an overvoltage event to protect upstream and downstream devices. The ISL71831SEH is available in a 48 Ld CQFP and operates across the extended temperature range of -55°C to +125°C. There is also a 16-channel version available offered in a 28 Ld CDFP, please refer to the ISL71830SEH datasheet for more information. For a list of differences please refer to Table 1 on page 2. Related Literature • TR017, “Single Event Effects (SEE) Testing of the ISL71831SEH” • UG040, “ISL71831SEHEV1Z Evaluation Board User Guide” • TR021, “Total Dose Testing of the ISL71831SEH 5V 32-Channel Analog Multiplexer” Features • DLA SMD# 5962-15248 • Fabricated using P6 SOI process technology • Rail-to-rail operation • No latch-up • Low rDS(ON). . . . . . . . . . . . . . . . . . . . . . . . . .<120Ω (maximum) • Single supply operation. . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V - Adjustable logic threshold control • Cold sparing capable . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V • Analog overvoltage range . . . . . . . . . . . . . . . . . . . . -0.4V to 7V • Switch input off leakage . . . . . . . . . . . . . . . . . . . . . . . . . 120nA • Transition times (tAHL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ns • Internally grounded metal lid • Break-before-make switching • ESD protection ≥5kV (HBM) • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation tolerance - Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .75krad(Si) - SEL/SEB LETTH (V+ = 6.3V) . . . . . . . . . . . . . 60MeV•cm2/mg NOTE: All lots are assurance tested to 75krad (0.01rad(Si)/s) wafer-by-wafer. Applications • Telemetry signal processing • Harsh environments • Down-hole drilling ISL71831SEH IN01 IN02 IN03 . . . IN32 OUT ADC 5 ADDRESS EN FIGURE 1. TYPICAL APPLICATION 90 80 +125°C 70 +25°C 60 50 40 30 -55°C 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 COMMON-MODE VOLTAGE (V) FIGURE 2. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V) December 10, 2015 FN8759.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 \| Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 1 page ISL71831SEH Electrical Specifications V+ = 5V, GND = 0V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) PARAMETER IOUT(OFF) DESCRIPTION Switch Output Off Leakage TEST CONDITIONS V+ = 5.5V, VOUT = 5V All inputs = 0.5V, TA = +25°C, -55°C TA = +125°C Post radiation, +25°C MIN MAX (Note 6) TYP (Note 6) -30 - 30 0 - 200 -30 - 30 UNIT nA nA nA V+ = 5.5V, VOUT = 0.5V All Inputs = 5V, TA = +25°C, -55°C TA = +125°C Post radiation, +25°C -30 - 30 -60 - 0 -30 - 30 nA nA nA IOUT(ON) Switch Output Leakage with Switch Enabled V+ = 5.5V, VIN = VOUT = 5V All unused inputs at 0.5V TA = +25°C, -55°C TA = +125°C Post radiation, +25°C -30 - 30 nA 0 - 200 nA -30 - 30 nA V+ = 5.5V, VIN = VOUT = 0.5V All unused inputs at 5V TA = +25°C, -55°C TA = +125°C Post radiation, +25°C -30 - 30 -60 - 0 -30 - 30 nA nA nA VIH/L IAH, IENH IAL, IENL ISUPPLY Logic Input Voltage High/Low Input Current with VAH, VENH Input Current with VAL, VENL Quiescent Supply Current V+ = 5.5V VREF = 3.3V V+ = 5.5V VEN = VA = VREF V+ = 5.5V VEN = VA = 0V V+ = VREF = VEN = 5.5V VA = 0V, TA = +25°C, -55°C TA = +125°C Post radiation, +25°C 1.3 - 1.6 -0.1 - 0.1 -0.1 - 0.1 - - 100 - - 500 - - 300 V µA µA nA nA nA IREF DYNAMIC Reference Quiescent Supply Current V+ = VREF = VEN = 5.5V VA = 0V - - 200 nA tAHL tBBM tEN(ON) tEN(OFF) VCTE VISO VCT CIN(OFF) COUT(OFF) Addressing Transition Time Break-Before-Make Delay Enable Turn-On Time Enable Turn-Off Time Charge Injection Off Isolation Crosstalk Input Capacitance Output Capacitance V+ = 4.5V; Figure 3 10 - 70 V+ = 4.5V; Figure 5 5 18 40 V+ = 4.5V; Figure 4 - - 40 V+ = 4.5V; Figure 4 - - 50 CL = 100pF, VIN = 0V, Figure 6 - 1.4 5.0 VEN = VREF, RL = open, f = 1kHz 60 - - VEN = 0V, f = 1kHz, VP-P = 1V RL = open f = 1MHz 73 - -- - 5 f = 1MHz - - 25 ns ns ns ns pC dB dB pF pF Submit Document Feedback 5 FN8759.1 December 10, 2015 5 Page ISL71831SEH Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, unless otherwise specified. 80 70 +25°C 60 50 +125°C 80 +125°C 70 60 50 40 40 30 -55°C 20 30 -55°C 20 +25°C 10 10 0 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 17. ADDRESS PROPAGATION DELAY (HIGH TO LOW) 0 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 18. ADDRESS PROPAGATION DELAY (LOW TO HIGH) 2V/DIV tADLH = 44.087ns tADHL = 34.382ns 1V/DIV 200ns/DIV FIGURE 19. ADDRESS PROPAGATION DELAY 40 35 30 25 20 15 10 5 0 3.0 -55°C 3.5 +125°C +25°C 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 FIGURE 20. BREAK-BEFORE-MAKE DELAY 5.5 2V/DIV 1V/DIV tBBM = 17.929ns 200ns/DIV FIGURE 21. BREAK-BEFORE-MAKE DELAY 60 50 40 +125°C 30 20 -55°C 10 +25°C 0 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 FIGURE 22. ENABLE TO OUTPUT PROPAGATION DELAY Submit Document Feedback 11 FN8759.1 December 10, 2015 11 Page

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